Research of simulation DPA for FPGA cryptographic chips

Computer Engineering and Applications ›› 2007, Vol. 43 ›› Issue (22): 103-105.

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Research of simulation DPA for FPGA cryptographic chips

DING Guo-liang，ZHAO Qiang，ZHU Jie，DENG Gao-ming

Dept. of Computer Engineering，Ordnance Engineering College，Shijiazhuang 050003，China

Received:1900-01-01 Revised:1900-01-01 Online:2007-08-01 Published:2007-08-01
Contact: DING Guo-liang

FPGA密码芯片差分功耗分析仿真研究

丁国良，赵强，禇杰，邓高明

军械工程学院计算机工程系，石家庄 050003

通讯作者: 丁国良

Abstract

Abstract: Through analyzing architectural features of FPGA，a power consumption model of FPGA on the basis of the mechanism for power consumption is put forward.A DPA simulation platform is realized for DPA to DES.The model and platform validate the vulnerability of the realization of DES with FPGA for DPA attacks.

Key words: side-channel attacks, power leakage model, Differential Power Analysis（DPA）, FPGA

摘要： 在分析FPGA组成结构特点的基础上，根据FPGA功耗产生的机理，提出了一种FPGA功耗模型。针对DES加密的DPA，实现了DPA仿真平台，并利用该模型和仿真平台验证了FPGA实现DES加密算法对DPA攻击的脆弱性。

关键词: 旁路攻击, 功耗泄漏模型, 差分功耗分析, FPGA

DING Guo-liang，ZHAO Qiang，ZHU Jie，DENG Gao-ming. Research of simulation DPA for FPGA cryptographic chips[J]. Computer Engineering and Applications, 2007, 43(22): 103-105.

丁国良，赵强，禇杰，邓高明. FPGA密码芯片差分功耗分析仿真研究[J]. 计算机工程与应用, 2007, 43(22): 103-105.

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Research of simulation DPA for FPGA cryptographic chips

FPGA密码芯片差分功耗分析仿真研究

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