Computer Engineering and Applications ›› 2021, Vol. 57 ›› Issue (20): 119-124.DOI: 10.3778/j.issn.1002-8331.2006-0355

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Research on Hardware Trojan Detection for FPGA Application

JIANG Peihe, WANG Chenxu, GUO Gang, WEI Yinsheng   

  1. 1.Shandong Fisherman Information Technology Co., Ltd., Weihai, Shandong 264200, China
    2.School of Opto-electronic Information Science and Technology, Yantai University, Yantai, Shandong 264005, China
    3.School of Electronics and Information Engineering, Harbin Institute of Technology, Harbin 150001, China
  • Online:2021-10-15 Published:2021-10-21



  1. 1.山东渔翁信息技术股份有限公司,山东 威海 264200
    2.烟台大学 光电信息科学技术学院,山东 烟台 264005
    3.哈尔滨工业大学 电子与信息工程学院,哈尔滨 150001


In recent years, the application of FPGA is more and more widespread. Hardware Trojans threaten the information security. In order to detect hardware Trojan and ensure the credibility of the FPGA, it proposes injection methods for hardware Trojans and ring oscillators by using smart compilation in Altera FPGA. Besides, a normalized algorithm for detecting and locating hardware Trojans is also raised. Based on this method, a hardware Trojan detection circuit based on ring oscillator is designed. According to the scale of the system, six ring oscillators are deployed and each of the ring oscillators consists of 121 NAND gates. Four typical hardware Trojans are implanted in the circuit successively, and a normalized algorithm is used to analyze the oscillation period of ring oscillator. Finally, all types of Trojan horses are located and detected. The detection results show that the detection method based on the ring oscillator can detect not only the hardware Trojan with large dynamic power consumption, but also the Trojan with small static power consumption. The proposed method can be applied to the actual FPGA project, and provides an effective way to find Trojan horse in time.

Key words: hardware Trojan, FPGA, ring oscillator, smart compilation, normalization algorithm


近年来,FPGA的应用愈加广泛。为确保FPGA中数据安全可信,在基于环形振荡器的硬件木马检测方法之上,提出一种在Altera FPGA中使用增量编译技术实现环形振荡器和木马植入的方法以及使用归一化差值算法发现并定位木马的数据分析方法。设计基于环形振荡器的硬件木马检测电路,根据系统规模共部署6级振荡环,每级环形振荡器由121个与非门构成。根据木马电路类型和功耗来源,在电路中依次植入四种典型硬件木马,使用归一化差值算法分析环形振荡器振荡频率,最终实现所有类型的木马定位与检测。检测结果表明,基于环形振荡器的硬件木马检测方法在FPGA中具有很好的木马检出效果,不仅能够检测具有较大动态功耗的木马,也可以完成对具有很小的静态功耗木马的检测。所提出的方法已经在实际FPGA工程中使用,为及时发现木马提供了一种有效途径。

关键词: 硬件木马, FPGA, 环形振荡器, 增量编译, 归一化差值算法