Performance Cost Modeling in Dynamic Reconfiguration Hardware Acceleration

doi:10.3778/j.issn.1002-8331.2102-0121

Abstract

Abstract: In recent years, with the continuous evolution of reconfigurable computing methods, the reconfigurable accelerator based on FPGA dynamic partial reconfigurable technology has become an important way to solve the problem of hardware resource limitation in traditional accelerator design. Different from traditional static reconstruction accelerators, the dynamic reconfiguration overhead of FPGA is a vital factor that affects the overall performance of hardware acceleration. However, there is still a lack of relevant methods that can accurately estimate the reconfiguration time in the early stages of reconfigurable hardware design. Therefore, this paper analyzes the bitstream configuration file of FPGA, proposes a method for estimating the size of the bitstream file based on the hardware resources consumed by the reconfigurable functional module, and builds a performance cost model of run-time reconfiguration on this basis. Then, a corresponding performance cost model of run-time is introduced based on the calculation/storage properties for the reconfigurable functional module. As a verification, a spectrum of algorithms, such as Winograd, FFT, GEMM algorithm in the neural network, and AES, DES in encryption, is deployed in dynamic reconstruction mode on the Xilinx VC709 FPGA platform. Experimental results show that the proposed performance cost model can quickly evaluate the dynamic reconfiguration overhead of different algorithms and achieves an average accuracy of 98%, which can be conveniently applied to the design of dynamic reconfiguration hardware acceleration.

Key words: dynamic reconfiguration, cost model, field programmable gate array（FPGA）, hardware acceleration

摘要： 近年来，随着可重构计算方法和可重构硬件特性的不断演进，基于FPGA动态部分重构技术构建运行时可重构加速器已经成为解决传统加速器设计中硬件资源限制问题的重要途径。然而，区别于传统静态重构加速器，FPGA的动态重构开销是影响硬件加速整体性能的重要因素，而目前尚缺少能够在可重构硬件设计的早期阶段进行动态重构开销精确估算的相关方法。为此，通过对主流FPGA的比特流配置文件进行剖析，提出了一种基于可重构功能模块消耗的资源估算相应部分重构比特流文件大小的方法，并在此基础上构建了运行时重构的性能开销模型。作为验证，在Xilinx VC709 FPGA平台对神经网络计算方法如Winograd算法、FFT算法、GEMM算法和加密算法如AES、DES等进行了动态重构模式下的硬件部署。实验结果表明，所提出的性能开销模型可以对不同算法的动态重构开销进行快速评估，并达到了平均98%的准确率，能够便捷地应用于动态重构加速器设计中。

关键词: 动态重构, 代价模型, 现场可编程门阵列（FPGA）, 硬件加速

YUAN Fuli, GONG Lei, LOU Wenqi, CHEN Xianglan. Performance Cost Modeling in Dynamic Reconfiguration Hardware Acceleration[J]. Computer Engineering and Applications, 2022, 58(6): 69-79.

苑福利, 宫磊, 娄文启, 陈香兰. 动态重构硬件加速中的性能开销建模[J]. 计算机工程与应用, 2022, 58(6): 69-79.

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