FPGA Implementation of Full-Universal AES Encryption Algorithm

doi:10.3778/j.issn.1002-8331.1908-0452

Abstract

Abstract:

A full-universal AES（Advanced Encryption Standard） encryption algorithm is proposed for the AES algorithm to be compatible with different working modes and different key lengths. The algorithm implements 128/192/256-bit wide encryption by designing an adjustable key expansion module, and supports the ECB/CBC/CFB/OFB/CTR 5 operating modes by the mode selection module. Based on Xilinx’s XC7VX690T FPGA simulation, the resource consumption is 1947 Slices, and the maximum operating frequency is 348.191 MHz.

Key words: AES encryption algorithm, non-pipeline, key expansion, Field-Programmable Gate Array（FPGA）

摘要：

针对高级加密标准（Advanced Encryption Standard，AES）算法需要兼容不同工作模式以及不同密钥长度的加密需求，提出全通用AES加密算法。该算法通过设计可调节密钥扩展模块和模式选择模块，实现128/192/256位宽的加密，支持ECB/CBC/CFB/OFB/CTR 5种工作模式。基于Xilinx公司的XC7VX690T FPGA综合仿真，资源消耗为1 947 Slices，最高工作频率为348.191 MHz。

关键词: AES加密算法, 非流水线, 密钥扩展, 现场可编程门阵列（FPGA）

LI Chiyang, LEI Qianqian, YANG Yanfei. FPGA Implementation of Full-Universal AES Encryption Algorithm[J]. Computer Engineering and Applications, 2020, 56(10): 83-87.

李炽阳，雷倩倩，杨延飞. 全通用AES加密算法的FPGA实现[J]. 计算机工程与应用, 2020, 56(10): 83-87.

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FPGA Implementation of Full-Universal AES Encryption Algorithm

全通用AES加密算法的FPGA实现

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