Abstract: Floorplanning is a fundamental problem in the design process of modern complex chips. It is the highest level of the physical design process. In many applications, while a good floorplan is needed, not all modules' infor- mation is available, or part of the provided information is inaccurate. Hence, we consider solving floorplanning of uncertain modules which are designed in front end system level and have not been designed completely yet. In this paper, to evaluate chip area effectively and efficiently, a non-slicing uncertain floorplan algorithm based on corner block list is proposed. The simulated annealing procedure is embedded. Experimental results on uncertain floor- planning show that our algorithm is efficiency and effectiveness. Within 30% input uncertainty, the area estimate derivation is about 1%.

Key words: VLSI, corner block list, uncertain modules, floorplanning

摘要： 布图规划是VLSI/SoC设计的重要步骤之一。为了缩短设计周期，在设计阶段的早期，也就是在模块物理信息没有完全确定之前就要进行布图规划，从而能估计出所设计的芯片的有关性能。因此，就必须开展不确定模块的布图规划研究。在本文中，提出了一种基于角模块链(Corner Block List，CBL)的不确定模块布图规划算法，采用模拟退火算法进行优化。实验结果表明，对于系统中有30％的模块信息不确定时，所获得的面积方差在1％左右，表明本算法是有效的。

关键词: VLSI, 角模块链, 不确定模块, 布图规划