Computer Engineering and Applications ›› 2009, Vol. 45 ›› Issue (29): 75-77.DOI: 10.3778/j.issn.1002-8331.2009.29.021

• 研发、设计、测试 • Previous Articles     Next Articles

Low I/O bandwidth and high throughput architecture design of motion estimation

CHEN Xi,LU Jie-cheng,XU Lei   

  1. Department of Electronic Science and Technology,University of Science and Technology of China,Hefei 230026,China
  • Received:2008-11-17 Revised:2009-02-18 Online:2009-10-11 Published:2009-10-11
  • Contact: CHEN Xi

低I/O带宽高性能运动估计VLSI结构的设计

陈 希,卢结成,徐 雷   

  1. 中国科学技术大学 电子科学与技术系,合肥 230026
  • 通讯作者: 陈 希

Abstract: Full search architecture is popular in motion estimation of video coding.Unfortunately,calculating by conventional 1-D、2-D systolic array or tree architecture will result in high I/O bandwidth,low efficiency.Using data-interlacing method,a new data flow and corresponding two-dimensional systolic array are proposed.They can efficiently reuse data to decrease I/O bandwidth with high throughput.Simulation shows that it can get 41 MVs in 256 cycles with only 3 I/O data ports.

Key words: video coding, motion estimation, Very Large Scale Integrated circuits(VLSI), Sum of Absolute Difference(SAD) reuse

摘要: 在视频编码的运动估计运算中,全搜索结构最为主流,然而相应传统的全搜索1-D、2-D脉动结构或树形结构在计算的过程中,往往会出现I/O带宽大或计算效率低等问题。针对这些问题,提出一种新的数据流和相应的两维脉动阵列结构,利用相邻当前块搜索域的数据重合,在保证高性能的同时最大程度地减小I/O带宽。结果表明,提出的结构可以在256周期内完成一个宏块41个运动矢量计算,并且只有3个数据输入。

关键词: 视频编码, 运动估计, 超大规模集成电路(VLSI), 绝对差和(SAD)重用

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