Abstract: A fast parallelable multiplier architecture over GF（2^m） is presented based on the reconfigurable most significant bit serial multiplier.One control signal and six two-way muxes are added in the multiplier，and it can use the fixed hardware resource to compute two multiplication parallelly，when the field length is less than half of the maximum.The proposed multiplier architecture has low circuit complexity and low power cost.It can use limited registers to accelerate computing，and also can be applied to the serial-parallel architecture.It suits the VLSI design of reconfigurable cryptographic applications with limited storage and low hardware complexity.

摘要： 在可重构的高位优先串行乘法器基础上，提出了一种GF（2^m）上可控制的快速乘法器结构。该乘法器增加了1个控制信号和7个两路选择器，在域宽小于最大域宽的一半时能利用现有硬件资源并行计算两个乘法。该乘法器结构电路复杂度低，能利用现有存储空间并行计算，并能扩展应用于串并混合结构中。这种乘法器适合存储空间小、低硬件复杂度的可重构密码系统VLSI设计。