Abstract: To make up for the loss or lack of ellipse accelerating function in embedded systems of 2D graphics acceleration, a design of an ellipse hardware accelerating unit is proposed. The unit supports complete function of ellipse drawing and filling. Using the top-down design method, the overall architecture of the unit is defined and divided into different function modules according to functional requirements. Pipelines are adopted to control operations among modules and decompose the graphics into horizontal line segments to output. Proper algorithms applicable for hardware implementation in this design are proposed and converted to logic designs using Verilog HDL. After simulation completed, the design is synthesized and implemented on FPGA. Simulation and debug results show that all the algorithms used are feasible, and the ellipse accelerating unit can correctly and quickly complete ellipse drawing and filling with various parameters configuration combinations. It’s proved that this design can well satisfy the requirements of embedded 2D graphics acceleration systems.

Key words: 2D-graphic, ellipse, fill, Field-Programmable Gate Array（FPGA）

摘要： 针对现有的嵌入式二维图形加速系统中椭圆加速功能缺失或者不足的缺陷，提出了一种支持椭圆绘制和填充的功能齐全的椭圆硬件加速单元设计方案。采用自顶向下的设计方法，根据功能需求定义了椭圆加速单元的总体结构及功能模块划分，内部各功能单元采用流水线控制，将图形分解成水平线段输出；提出了适用于本设计的图形硬件实现算法，用Verilog HDL语言编写代码完成各模块的逻辑设计；通过仿真后在FPGA上综合实现。仿真及调试结果表明：提出的图形算法切实可行；设计的椭圆硬件加速单元能够正确快速地完成各种椭圆参数配置组合的椭圆绘制和填充功能，能够很好地满足二维图形加速系统的需求。

关键词: 二维图形, 椭圆, 填充, 现场可编程门阵列（FPGA）