Research of reconfigurable Gr?stl algorithm on FPGA platform

Computer Engineering and Applications ›› 2012, Vol. 48 ›› Issue (6): 49-52.

• 研发、设计、测试 • Previous Articles Next Articles

Research of reconfigurable Gr?stl algorithm on FPGA platform

LI Zhican1, WANG Yi1，2，3, LI Renfa1，2，3

1.Embedded System and Network Laboratory, Hunan University, Changsha 410082, China
2.Graduate Innovation Base, Hunan University, Changsha 410082, China
3.Hunan Province Key Laboratory of Network and Information Security, Hunan University, Changsha 410082, China

Received:1900-01-01 Revised:1900-01-01 Online:2012-02-21 Published:2012-02-21

可重构Gr?stl设计研究及其FPGA实现

李志灿1，王奕1，2，3，李仁发1，2，3

1.湖南大学嵌入式系统与网络实验室，长沙 410082
2.湖南大学湖南省研究生培养创新基地，长沙 410082
3.湖南大学网络与信息安全湖南省重点实验室，长沙 410082

Abstract

Abstract: Gr?stl algorithm is one of SHA-3 finalist which is mainly composed of Message Digest（MD） iteration and AES compression function. Previous research work has been done on hardware implementation of Gr?stl algorithm, but the disadvantage of their implementation lies on only focusing on one or two parameters version of Gr?stl and less flexibility. Base on the analysis of Gr?stl algorithm, this paper proposes a new reconfigurable architecture which can support four different parameters of Gr?stl algorithms. The proposed design ports to Xilinx Virtex-5 FPGA platform and achieved 223.32 MHz clock frequency using 4 279 slices. The experimental results show that the proposed design has smaller size, higher clock frequency and more flexibility supporting compared with the existing work when ports to FPGA platform.

Key words: Secure Hash Algorithm（SHA）, reconfigurability, Field-Programmable Gate Array（FPGA）, Gr?stl algorithm

摘要： Gr?stl是继承MD迭代结构和沿用AES压缩函数的SHA-3候选算法。目前的研究只针对Gr?stl算法的一种或两种参数版本进行实现，并没有针对Gr?stl四种参数版本的设计，缺少灵活性。在分析Gr?stl算法的基础上，采用可重构的设计思想，在FPGA上实现了Gr?stl四种参数版本。实验结果表明，在Xilinx Virtex-5 FPGA平台上，四参数可重构方案的面积为4 279 slices，时钟频率为223.32 MHz，与已有的实现方法相比，具有面积小、时钟频率高及灵活性等优点。

关键词: 安全散列算法（SHA）, 可重构, 现场可编程门阵列（FPGA）, Gr?stl算法

LI Zhican1, WANG Yi1，2，3, LI Renfa1，2，3. Research of reconfigurable Gr?stl algorithm on FPGA platform[J]. Computer Engineering and Applications, 2012, 48(6): 49-52.

李志灿1，王奕1，2，3，李仁发1，2，3. 可重构Gr?stl设计研究及其FPGA实现[J]. 计算机工程与应用, 2012, 48(6): 49-52.

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Research of reconfigurable Gr?stl algorithm on FPGA platform

可重构Gr?stl设计研究及其FPGA实现

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