Abstract: To support HDTV application, a high performance CABAC hardware decode architecture is proposed in this paper. Through the high performance SRAM organization, the decoder improve the SRAM access efficiency at the same time reduce the SRAM area. The high efficient decoder architecture make it possible that 1bit syntax element can be decoded in one clock cycle, and the decoding speed improved compare with current decoder and software. So the decoder can satisfy the decoding speed of main profile H.264 bits stream based on HDTV application by fully hardware.

摘要： 针对高清晰数字电视应用，提出了一种针对H.264标准的CABAC硬件解码器结构。通过高效的SRAM组织，在提高解码器访问SRAM的效率的同时减小了SRAM的面积。高效的解码器架构设计，使得每一个时钟周期可解码1bit的语法元素，与软件和现有解码器相比提高了解码速度。可以通过全硬件的方式解码基于主规范(main profile)的H.264码流，满足高清晰数字电视的要求。