[1] |
LENG Ming, SUN Lingyu, GUO Chen.
Forward Circuit Generation Algorithm of XDL Netlist
[J]. Computer Engineering and Applications, 2021, 57(10): 75-80.
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[2] |
WU Yiyang, FAN Fan, ZHOU Yi, HUANG Jun.
FPGA Implementation of Affine Transformation Based on Pre-interpolation
[J]. Computer Engineering and Applications, 2020, 56(6): 224-230.
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[3] |
WANG Meile, ZHANG Zhizhong, XI Bing.
Feasibility Analysis of Downlink Baseband Board for LTE-A Air Interface Analyzer
[J]. Computer Engineering and Applications, 2020, 56(4): 268-273.
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[4] |
WU Bo, WU Jing, LUO Wei, ZHU Jie.
Service-Related Routing Method Based on Programmable Data Plane
[J]. Computer Engineering and Applications, 2020, 56(3): 106-112.
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[5] |
ZHANG Wei, LIU Yuhong, ZHANG Rongfen.
Design of IP Cores for CNN Convolutional Layer and Pooling Layer Capable of Time Division Multiplexing
[J]. Computer Engineering and Applications, 2020, 56(24): 66-71.
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[6] |
WU Jin, ZHANG Weihua, XI Meng, DAI Wei.
Optimized Design and FPGA Implementation of High-Performance Face Recognition Accelerator
[J]. Computer Engineering and Applications, 2020, 56(22): 48-54.
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[7] |
WANG Fan, ZHOU Guoqing, ZHANG Rongting, LIU Dequan.
FPGA-Oriented Fast Connected Component Labeling Method
[J]. Computer Engineering and Applications, 2020, 56(22): 230-235.
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[8] |
LI Zenggang, WANG Zhengyan, SUN Jingcheng.
Research and Design of Handwritten Digital BP Neural Network Based on FPGA
[J]. Computer Engineering and Applications, 2020, 56(17): 251-257.
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[9] |
LI Rengang, REN Zhixin, WANG Jiangwei, KAN Hongwei, ZHANG Chuang, GONG Weifeng.
Design and Implementation of Memory Data Protection Technology Based on FPGA
[J]. Computer Engineering and Applications, 2020, 56(13): 72-76.
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[10] |
SUN Jingcheng, WANG Zhengyan, LI Zenggang.
FPGA Implementation of Convolution Neural Network Digital Recognition System
[J]. Computer Engineering and Applications, 2020, 56(13): 181-188.
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[11] |
LI Chiyang, LEI Qianqian, YANG Yanfei.
FPGA Implementation of Full-Universal AES Encryption Algorithm
[J]. Computer Engineering and Applications, 2020, 56(10): 83-87.
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[12] |
WANG Haiyu, XIE Lili, WANG Shan.
Neural Network Sinusoidal Signal Generator
[J]. Computer Engineering and Applications, 2019, 55(16): 259-264.
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[13] |
PENG Fulai, YU Zhilou, CHEN Naikuo, GENG Shihua, LI Kaiyi.
Reconfigurable computing system design and performance exploration towards to domestic CPU
[J]. Computer Engineering and Applications, 2018, 54(23): 36-41.
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[14] |
WANG Weiting1,2, LI Jinjie2, ZHANG Wenxu1.
Research of implementing DDS without phase truncation spur based on phase code compensation
[J]. Computer Engineering and Applications, 2017, 53(4): 244-250.
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[15] |
FENG Binbin1, JIANG Xinhua1,2, LIN Junjie2, NIE Mingxing2.
Research and implementation of real-time semi global matching algorithm based on FPGA stereo vision
[J]. Computer Engineering and Applications, 2017, 53(22): 163-168.
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