Computer Engineering and Applications ›› 2021, Vol. 57 ›› Issue (3): 80-86.DOI: 10.3778/j.issn.1002-8331.2002-0347

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Research and Design of FPU Based on RISC-V Floating Point Instruction Set

PAN Shupeng, LIU Youyao, JIAO Jiye, LI Zhao   

  1. 1.School of Electronic Engineering, Xi’an University of Posts &Telecommunications, Xi’an 710121, China
    2.School of Computer Science & Technology, Xi’an University of Posts & Telecommunications, Xi’an 710121, China
  • Online:2021-02-01 Published:2021-01-29



  1. 1.西安邮电大学 电子工程学院,西安 710121
    2.西安邮电大学 计算机学院,西安 710121


Aiming at the problems that the speed of floating-point arithmetic which is implemented by software, cannot meet the real-time requirements of embedded processors, and has limited operation types now, a floating-point processor based on the RISC-V instruction set is proposed, which can perform addition, subtraction, multiplication, division, square root, multiply-accumulate, and comparison operations, which fully complies with the IEEE 754-2008 standard. The function of the floating-point processor is verified in the VCS simulation environment, each module can meet the correctness requirements. The floating-point processor is integrated with an open source processor core Hummingbird E203, logic synthesis is completed using the SMIC 0.18 process library, and the design is tested on the FPGA. The results show that the number of logic gates of the floating-point processor is only 24,200 and the throughput is 150 MFLOPS. Compared with the design of published documents, the hardware area is reduced by 7% and 1.5%, respectively. The comprehensive operating frequency can reach 100 MHz.

Key words: floating-point processor, RISC-V instruction set, microprocessor, IEEE 754-2008 standard, logic synthesis


针对目前浮点运算软件实现速度慢,不能满足嵌入式处理器实时性要求以及运算种类有限等问题,提出了一种基于RISC-V指令集的浮点处理器,能够执行加法、减法、乘法、除法、平方根、乘累加以及比较运算,完全符合IEEE 754-2008标准。在VCS仿真环境下对浮点处理器进行了功能验证,各模块均能满足正确性要求。将浮点处理器与一款开源处理器核蜂鸟E203集成,使用SMIC 0.18工艺库完成了逻辑综合,并在FPGA上对设计进行了测试。结果表明,该浮点处理器的逻辑门数仅为24 200,吞吐量为150 MFLOPS,与已公开文献的设计方案相比,硬件面积分别减少7%、1.5%。综合运行频率可达100 MHz。

关键词: 浮点处理器, RISC-V指令集, 微处理器, IEEE 754-2008标准, 逻辑综合