%0 Journal Article %A PAN Shupeng %A LIU Youyao %A JIAO Jiye %A LI Zhao %T Research and Design of FPU Based on RISC-V Floating Point Instruction Set %D 2021 %R 10.3778/j.issn.1002-8331.2002-0347 %J Computer Engineering and Applications %P 80-86 %V 57 %N 3 %X

Aiming at the problems that the speed of floating-point arithmetic which is implemented by software, cannot meet the real-time requirements of embedded processors, and has limited operation types now, a floating-point processor based on the RISC-V instruction set is proposed, which can perform addition, subtraction, multiplication, division, square root, multiply-accumulate, and comparison operations, which fully complies with the IEEE 754-2008 standard. The function of the floating-point processor is verified in the VCS simulation environment, each module can meet the correctness requirements. The floating-point processor is integrated with an open source processor core Hummingbird E203, logic synthesis is completed using the SMIC 0.18 process library, and the design is tested on the FPGA. The results show that the number of logic gates of the floating-point processor is only 24,200 and the throughput is 150 MFLOPS. Compared with the design of published documents, the hardware area is reduced by 7% and 1.5%, respectively. The comprehensive operating frequency can reach 100 MHz.

%U http://cea.ceaj.org/EN/10.3778/j.issn.1002-8331.2002-0347