Design and FPGA implementation for high-speed RS coding and decoding

Computer Engineering and Applications ›› 2012, Vol. 48 ›› Issue (1): 64-67.

• 研发、设计、测试 • Previous Articles Next Articles

Design and FPGA implementation for high-speed RS coding and decoding

XIANG Liangjun1, WANG Zibin1, JIN Guoping2, ZHENG Linhua1

1.College of Electronic Science and Engineering, National University of Defense Technology, Changsha 410073, China
2.Universal Information Development Center, Beijing 100094, China

Received:1900-01-01 Revised:1900-01-01 Online:2012-01-01 Published:2012-01-01

高速RS编译码器的设计及其FPGA实现

向良军1，王梓斌1，金国平2，郑林华1

1.国防科技大学电子科学与工程学院，长沙 410073
2.北京环球信息应用开发中心，北京 100094

Abstract

Abstract: This paper analyzes the principle of RS coding and decoding. It deeply investigates the multiplier circuit of the coding. BM iteration algorithm for computing error position polynomial and error value polynomial is also improved. Syndrome computation and chain search circuits adapted to FPGA hardware are presented. The implementation results show that hardware resource is occupied on 15% for implementing coding and decoding of （31, 15） RS code on XC4VSX35 FPGA chip owned by Xilinx and decoding speed can reach to 10 Mb/s on condition that system clock is 200 MHz indicated to high-speed data process.

Key words: Reed-Solomon（RS） coding and decoding, Field-Programmable Gate Array（FPGA）, Galois Field（GF） multiplier, iteration decoding algorithm

摘要： 在分析RS（Reed-Solomon）码编译码基本原理的基础上，对编码过程中的乘法电路实现进行了深入分析，对译码过程中用于错误位置多项式和错误值多项式计算的BM（Berlekamp-Massey）迭代算法进行改进，并设计了适合于FPGA硬件实现的伴随式计算策略和钱搜索电路。硬件实现结果表明，改进算法能有效节省硬件资源，在Xilinx公司的XC4VSX35 FPGA上仅需要总资源的15%就可以实现（31，15）RS码编译码器电路，且在200 MHz系统时钟频率时达到10 Mb/s的译码速率，实现了高速数据处理。

关键词: 里所（RS）编译码, 现场可编程门阵列（FPGA）, 域乘法, 迭代译码算法

XIANG Liangjun1, WANG Zibin1, JIN Guoping2, ZHENG Linhua1. Design and FPGA implementation for high-speed RS coding and decoding[J]. Computer Engineering and Applications, 2012, 48(1): 64-67.

向良军1，王梓斌1，金国平2，郑林华1. 高速RS编译码器的设计及其FPGA实现[J]. 计算机工程与应用, 2012, 48(1): 64-67.

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Design and FPGA implementation for high-speed RS coding and decoding

高速RS编译码器的设计及其FPGA实现

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