Design of 3 GHz bandwidth digital-correlator

doi:10.3778/j.issn.1002-8331.2011.01.016

Computer Engineering and Applications ›› 2011, Vol. 47 ›› Issue (1): 56-59.DOI: 10.3778/j.issn.1002-8331.2011.01.016

• 研发、设计、测试 • Previous Articles Next Articles

Design of 3 GHz bandwidth digital-correlator

LU Hao^1，2，WANG Zhenzhan¹

1.Center for Space Science and Applied Research，Chinese Academy of Sciences，Beijing 100190，China
2.Graduate University of Chinese Academy of Sciences，Beijing 100049，China

Received:2010-07-15 Revised:2010-09-15 Online:2011-01-01 Published:2011-01-01
Contact: LU Hao

3 GHz带宽数字相关器设计

陆浩^1，2，王振占¹

1.中国科学院空间科学与应用研究中心，北京 100190
2.中国科学院研究生院，北京 100049

通讯作者: 陆浩

Abstract

Abstract: To get all the four Stokes parameters and ocean surface field，a 3 GHz bandwidth digital correlator used in polarization radiometer is introduced.Four high-speed A/D Converters（ADC083000） are used to sample four signal channels at the same time.The sampling results are operated in the newest Field-Programmable Gate Array（FPGA）-Virtex5 from Xilinx to make correlation calculation with correlation results translated to computer through serial port.The structure of interfacing circuit and control system of the main modules are presented in detail.For dual polarimetric channels in radiometer，the system max sampling rate is 3 GHz and the resolution is 8 bit.

Key words: high-speed Analog Digital Converter（ADC）, Field-Programmable Gate Array（FPGA）, digital correlation, fully polarimetric microwave radiometer

摘要： 为完成四个Stokes矢量参数的测量，反演海面风场，提出了数字极化辐射计中3 GHz带宽数字相关器的设计方法。首先分析了高速数据采样和相关处理系统。四路信号数据采样通过四片A/D转换器（ADC083000）完成，采样结果传输到Xilinx公司新一代现场可编程门阵列（FPGA）-Virtex5芯片作数据的多路复用和相关运算，相关结果通过串口上传到计算机。详细介绍了系统结构、数据流程和各部分接口电路的设计。系统可以实现辐射计中双极化通道8 bit量化3 GHz带宽的相关计算。

关键词: 高速模数转换器, 现场可编程门阵列, 数字相关, 全极化微波辐射计

CLC Number:

TP274

LU Hao^1，2，WANG Zhenzhan¹. Design of 3 GHz bandwidth digital-correlator[J]. Computer Engineering and Applications, 2011, 47(1): 56-59.

陆浩^1，2，王振占¹. 3 GHz带宽数字相关器设计[J]. 计算机工程与应用, 2011, 47(1): 56-59.

[1]	WANG Meile, ZHANG Zhizhong, XI Bing. Feasibility Analysis of Downlink Baseband Board for LTE-A Air Interface Analyzer [J]. Computer Engineering and Applications, 2020, 56(4): 268-273.
[2]	LI Chiyang, LEI Qianqian, YANG Yanfei. FPGA Implementation of Full-Universal AES Encryption Algorithm [J]. Computer Engineering and Applications, 2020, 56(10): 83-87.
[3]	PENG Fulai, YU Zhilou, CHEN Naikuo, GENG Shihua, LI Kaiyi. Reconfigurable computing system design and performance exploration towards to domestic CPU [J]. Computer Engineering and Applications, 2018, 54(23): 36-41.
[4]	WANG Kai，SHI Longzhao. Design and implementation of fast connected component labeling algorithm based on FPGA [J]. Computer Engineering and Applications, 2016, 52(18): 192-198.
[5]	XIE Zhoubiao1, ZHOU Yi2, LONG Bin3. Research on ellipse hardware accelerating algorithm and its FPGA implementation [J]. Computer Engineering and Applications, 2015, 51(3): 45-49.
[6]	ZHANG Li1, ZHOU Fan1, HU Yinfeng2. Real-time image data transposition method for high-speed digital inkjet printer [J]. Computer Engineering and Applications, 2014, 50(6): 35-39.
[7]	MA Shengqian, YANG Yang, LIU Juanfang. Adaptive low pass filter circuit implemented by ADPLL [J]. Computer Engineering and Applications, 2014, 50(3): 181-184.
[8]	YANG Jianfeng, ZHANG Feng, ZHANG Cui. Strategy of speed-controlled signal of multi-channel PWM based on ROM of FPGA [J]. Computer Engineering and Applications, 2014, 50(20): 244-248.
[9]	WANG Zhibin, YANG Wenmin, ZHANG Yuanpu, CHAI Zhilei. Dense optical flow software-hardware co-processing based on ZYNQ [J]. Computer Engineering and Applications, 2014, 50(18): 44-49.
[10]	LI Zhican1, WANG Yi1，2，3, LI Renfa1，2，3. Research of reconfigurable Gr?stl algorithm on FPGA platform [J]. Computer Engineering and Applications, 2012, 48(6): 49-52.
[11]	ZHU Xueliang, CHAI Zhilei, LIANG Jiuzhen, ZHONG Chuanjie. Study and implementation of FPGA-based KLT algorithm for fabric inspection system [J]. Computer Engineering and Applications, 2012, 48(24): 144-148.
[12]	XIANG Liangjun1, WANG Zibin1, JIN Guoping2, ZHENG Linhua1. Design and FPGA implementation for high-speed RS coding and decoding [J]. Computer Engineering and Applications, 2012, 48(1): 64-67.
[13]	CHEN Xiaoming, LI Binhua. VHDL design of EMCCD timing generator [J]. Computer Engineering and Applications, 2012, 48(1): 72-75.
[14]	SONG Qingzeng1，GU Junhua2，ZHANG Jinzhu3. Research on FPGA-based Jacobi iterative solver [J]. Computer Engineering and Applications, 2011, 47(29): 74-77.
[15]	LI Rui，TAO Liang. FPGA-based simulation and design of parallel algorithm for multirate-based discrete Gabor transform [J]. Computer Engineering and Applications, 2011, 47(13): 50-51.

Design of 3 GHz bandwidth digital-correlator

3 GHz带宽数字相关器设计

PDF

Knowledge

Abstract

Cite this article

share this article

References

Related Articles 15

Recommended Articles

Metrics