LIU Youyao, PAN Yuchen. Optimal Design of Parameterized Superscalar Processor Based on RISC-V[J]. Computer Engineering and Applications, 2022, 58(5): 66-74.
[1] ANDREW W,YUNSUP L,DAVID A P,et al.The RISC-V instruction set manual,volume I:user-level ISA,version 2.0:UCB/EECS-2014-54[R].Berkeley,USA:University of California.EECS Department,2014.
[2] GALA N,MENON A,BODDUNA R,et al.SHAKTI processors:an open-source hardware initiative[C]//2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems(VLSID),Kolkata,2016:7-8.
[3] KELLER B.A RISC-V processor SoC with integrated power management at submicrosecond timescales in 28 nm FD-SOI[J].IEEE Journal of Solid-State Circuits,2017,52(7):1863-1875.
[4] H?LLER R,HASELBERGER D.Open-source RISC-V processor IP cores for FPGAs—overview and eval-uation[C]//2019 8th Mediterranean Conference on Embedded Computing(MECO),Budva,Montenegro,2019:1-6.
[5] JAIN V,SHARMA A,BEZERRA E A.Implementation and extension of bit manipulation instruction on RISC-V architecture using FPGA[C]//2020 IEEE 9th International Conference on Communication Systems and Network Technologies(CSNT),Gwalior,India,2020:167-172.
[6] HEINZ C,LAVAN Y,HOFMANN J,et al.A catalog and in-hardware evaluation of open-source drop-in compatible RISC-V softcore processors[C]//2019 International Conference on ReConFigurable Computing and FPGAs(ReConFig),Cancun,Mexico,2019:1-8.
[7] CELIO C,PATTERSON D A,ASANOVI? K.The Berkeley Out-of-Order Machine(BOOM):an industry competitive,synthesizable,parameterized RISC-V processor[R].Berkeley:University of California.EECS Department,2015.
[8] BACHRACH J.Chisel:constructing hardware in a scala embedded language[C]//DAC Design Automation Conference,San Francisco,CA,2012:1212-1221.
[9] GOODACRE J,SLOSS A N.Parallelism and the ARM instruction set architecture[J].Computer,2005,38(7):42-50.
[10] SMITH J E,PLESZKUN A R.Implementing precise interrupts in pipelined processors[J].IEEE Transactions on Computers,1988,37(5):562-573.
[11] PATIL V,RAVEENDRAN A,SOBHA P M,et al.Out of order floating point coprocessor for RISC V ISA[C]//2015 19th International Symposium on VLSI Design and Test,2015:1-7.
[12] HE J,KO S.High-performance RISC-V processor with improved dispatch and commit schemes[C]//2020 International Conference on Electronics,Information,and Communication(ICEIC),Barcelona,Spain,2020:1-4.
[13] MARTI S P,BORRAS J S.A complexity-effective out-of-order retirement microarchitecture[J].IEEE Transactions on Computers,2009,58(12):1626-1639.
[14] 李昭,刘有耀,焦继业,等.超标量处理器乱序提交机制的研究与设计[J].计算机工程,2021,47(4):180-186.
LI Zhao,LIU Youyao,JIAO Jiye,et al.Research and design of out-of-order submission mechanism for superscalar processor[J].Computer Engineering,2021,47(4):180-186.
[15] WANG B,AKRAM A,LOWE-POWER J.FlexCPU:a configurable out-of-order CPU abstraction[C]//2019 IEEE International Symposium on Performance Analysis of Systems and Software(ISPASS),Madison,WI,USA,2019:147-148.
[16] ZHANG N,WEI X,CHEN L,et al.Three-level memory access architecture for FPGA-based[C]//2019 IEEE International Conference on Signal,Information and Data Processing(ICSIDP),Chongqing,China,2019:1-6.
[17] BELL G B,LIPASTI M H.Deconstructing commit[C]//Proceedings of the IEEE International Symposium on ISPASS Performance Analysis of Systems and Software.Austin,TX,USA:IEEE Press,2004:68-77.
[18] LEE J K F,SMITH A J.Branch prediction strategies and branch target buffer design[J].Computer,1984,17(1):6-22.
[19] ASHOUR H.Design,simulation and realization of a parametrizable,configurable and modular asynchronous FIFO[C]//2015 Science and Information Conference(SAI),London,2015:1391-1395.
[20] LEE K,JEONG I,RO W W.Parallel in-order execution architecture for low-power processor[C]//Proceedings of the International SoC Design Conference,Seoul,Korea,2017:65-66.
[21] ASADUZZAMAN A,SIBAI F N.Investigating cache parameters and locking in predictable and low power embedded systems[C]//2010 International Conference on Microelectronics,Cairo,2010:140-143.