Abstract: With the continuous improvement of deep submicron technology and chip operating rate, crosstalk noise becomes more and more serious. It is high time to test crosstalk delay. Based on combinational circuit, the SAT（Boolean satisfiability） method is introduced to the crosstalk induced delay test, and lexical analysis and syntax analysis are used to extract the formal model of a Verilog（Hardware Description Language） source code directly to combine into CNF （Conjunctive Normal Form）. Using non-robust tests, the crosstalk delay is activated, and CNF expressions are simplified. Finally, the testing vectors are obtained by inputting the SAT solver. By assessing on ISCAS’85 benchmark circuits, experimental results show that the algorithm is effective for crosstalk-induced delay faults.

Key words: Signal Integrity（SI）, crosstalk, SAT, delay faults testing

摘要： 随着深亚微米技术的不断发展和芯片运行速率的不断提高，串扰噪声问题越来越严重，对串扰时延测试已成为一个迫切的问题。在组合电路的基础上，将SAT（布尔可满足性）方法引入到串扰引起的时延测试中，通过词法分析和语法分析直接提取Verilog（硬件描述语言）源码的形式模型，组合成CNF（合取范式）形式。并在非鲁棒测试条件下，激活串扰时延故障，约简CNF范式表达式，最终输入SAT求解器得到测试矢量。在标准电路 ISCAS’85上进行实验验证，结果表明：该算法对于串扰时延故障的测试矢量产生是有效的。

关键词: 信号完整性, 串扰, 可满足性, 时延测试