Abstract: The circuit module of 2D lifting-structure based 9/7 Inverse Discrete Wavelet Transform （IDWT） is the key technology of the decoding and display and the real-time processing of the high resolution image. To improve the global performance of the circuit module, the principle theory of 2D lifting-structure 9/7 IDWT is studied. With the characters of the image data flow studied, the novel flipping-structure algorithm is proposed based on the circuit model. Further, the parallel processing VLSI architecture of multi-processor based on the proposed algorithm is designed, in which the critical path is reduced to one multiplier by pipeline and only 4N transfer memory is needed for a N×N image by the data flow re-organization so that the memory consumption and the processing speed are improved simultaneously. The circuit module is synthesized and verified on Sparten6-xc6slx150t FPGA, which shows that the system can operate smoothly at 166.34 MHz clock rate.

Key words: Inverse Discrete Wavelet Transform（IDWT）, flipping-structure, pipeline, low memory, parallel architecture

摘要： 采用提升结构的二维9/7离散小波逆变换模块是高清图像解码显示和实时处理的关键支撑技术。为实现电路模块的整体优化，在提升结构二维9/7离散小波逆变换标准算法的研究基础上，通过分析图像数据的输入输出顺序，结合器件模型提出一种翻转结构的优化算法。进一步地，给出了所提算法的一种多核并行VLSI结构：通过流水线技术将关键路径降为一级乘法器延迟；通过重组织数据流，处理N×N大小的图像仅需4N的中间缓存，从而在提升该模块速率的同时降低了中间缓存。基于Sparten6-xc6slx150t FPGA进行综合验证，结果表明该模块可稳定运行于166.34 MHz时钟速率。

关键词: 离散小波逆变换, 翻转结构, 流水线, 低内存, 并行结构