Abstract: MELP algorithm with low bit-rate is complexity，which makes implementation of MELP coder/decoder in real time very difficult.Based on the algorithm of MELP decoder，presents a SOC scheme for implementing a MELP decoder system on a FPGA chip，and the system has been verified on FPGA.The important parts of the system are NiosII processor and custom IP cores.The custom IP cores remedies the weak capability of NiosII processor.Experiments shows that MELP decoder is achievable in real time.

Key words: Mixed Excited Linear Predication（MELP）, real time, pipeline, IP core

摘要： 低比特率混合激励线性预测（MELP）算法的复杂性使得MELP声码器系统的实时实现比较困难。根据MELP声码器的算法，提出了一种新的基于现场可编程门阵列（FPGA）实现整个解码器系统的单片方案，并在FPGA平台上完成了对整个系统的验证。该系统主要包括NiosII微处理器和自定义IP模块，通过自定义IP弥补了NiosII处理器运算能力的不足。实验结果表明，实现了MELP解码系统的实时处理。

关键词: 混合激励线性预测, 实时, 流水线, IP模块