Abstract: This paper proposes a new simple and flexible architecture for JPEG2000 bit-plane coding，the architecture contains three state machines to control the coding process.By using local optimization and template technology for data buffering，the coding efficiency is improved.The new architecture has fewer hardware consumption and great flexibility in handling the code block.The Verilog HDL modules of architecture are designed，simulated and synthesized to FPGA，the results show that the architecture designed is correct and the highest frequency of the design is up to 82 MHz.

Key words: JPEG2000, bit-plane coding, Verilog HDL

摘要： 采用三个状态机控制编码操作，并采用局部优化和模板数据缓冲技术，提出了一种简单、灵活的新结构，提高了编码效率，减小了硬件实现的资源消耗，在码块处理上也具有很大灵活性。设计了硬件结构的Verilog HDL模型，进行了仿真和逻辑综合，并用FPGA进行了验证。仿真和综合结果表明，设计的硬件结构是正确的，最高频率可达82 MHz，满足设计要求。

关键词: JPEG2000, 位平面编码, Verilog HDL