Abstract: This paper develops a reduced IPv6 Stack based on FPGA，and analyzes the function of each module.The Verilog HDL model of the architecture is coded，simulated and synthesized.Then the design is verified by ALTERA FPGA.The results of the simulation and experiments indicate that the hardware implementation meets the design requirement，and it is more efficient for the small devices to connect to Internet.

Key words: Field Programmable Gate Array（FPGA）, IPv6, stack, Verilog HDL

摘要： 研究了IPv6精简协议栈的FPGA硬件实现，分析了各个模块的功能。编写了硬件结构的Verilog HDL模型，进行了仿真和逻辑综合，并成功用ALTERA的FGPA 对协议栈进行了验证。仿真和实验结果证明，所设计的硬件达到了设计要求，使小设备接入网络更加方便快捷。

关键词: 现场可编程门阵列, IPv6, 协议栈, Verilog HDL