Design and implementation of high-speed TLB

Computer Engineering and Applications ›› 2007, Vol. 43 ›› Issue (16): 1-3.

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Design and implementation of high-speed TLB

LIU Zong-lin，WU Hu-cheng，TANG Tao，DANG Gui-bin

School of Computer，National University of Defense Technology，Changsha 410073，China

Received:1900-01-01 Revised:1900-01-01 Online:2007-06-01 Published:2007-06-01
Contact: LIU Zong-lin

一种高速TLB的设计与实现

刘宗林，吴虎成，唐涛，党桂斌

国防科技大学计算机学院，长沙 410073

通讯作者: 刘宗林

Abstract

Abstract: A new high-speed TLB architecture is designed for accelerating the address transition rate from linear address to physical one in micro processors.Full custom circuit parts of CAM and SRAM are adopted. According to the output signal characteristic of the tow kinds of storage units，amplifying and reading circuits are elaborately designed to improve the reading speed of TLB. Taped out chips can work correctly and reliably，and can keep the transition delay at about 1 ns.

Key words: Translate Look-aside Buffer（TLB）, CAM, SRAM, replacement strategy, address transition

摘要： 为了加快微处理器中线性地址向物理地址转换的速度，提出了一种高速TLB结构。结构采用全定制的CAM阵列和SRAM阵列，并根据CAM和SRAM单元的输出特点设计了精巧的读出放大逻辑，有效提高了TLB的读出速度。经流片测试，表明设计正确可靠，能够保证地址转换延时在1 ns左右。

关键词: Translate Look-aside Buffer（TLB）, CAM, SRAM, 替换策略, 地址转换

LIU Zong-lin，WU Hu-cheng，TANG Tao，DANG Gui-bin. Design and implementation of high-speed TLB[J]. Computer Engineering and Applications, 2007, 43(16): 1-3.

刘宗林，吴虎成，唐涛，党桂斌. 一种高速TLB的设计与实现[J]. 计算机工程与应用, 2007, 43(16): 1-3.

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Design and implementation of high-speed TLB

一种高速TLB的设计与实现

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