Abstract: This paper presents a new selective trigger scan chain architecture by changing traditional scan design using a scan register，whose length is equal to that of scan chain.It can efficiently reduce dynamic power in shift cycle and increase the scan clock frequency.The test data that the architecture requires is difference test vector set，so a separate CSR（Cyclical Scan Register） isn’t required in decompression after encoding lengths of runs of 0s in the test data.Experiment results on ISCAS’89 benchmark circuits show that the proposed technique is more superior to reduce average power during scan test than traditional scan design.

Key words: scan chain, test power, selective trigger, difference vector

摘要： 利用一个和扫描链等长的扫描移位寄存器，对传统扫描链进行改造，提出了一种新型的选择触发的扫描链结构。它有效地降低了传统扫描链扫描移位过程中的动态功耗，并提高了扫描时钟频率，同时它所需要的测试数据为原始测试向量集的差分向量序列集合，编码压缩差分序列中连续“0”的测试数据后，在解压测试时不需要分离的CSR（Cyclical Scan Register，循环扫描移位寄存器）。在ISCAS’89基准电路上进行的实验表明，该方法与传统的串行扫描技术相比，能有效地降低扫描移位过程中的平均功耗。

关键词: 扫描链, 测试功耗, 选择触发, 差分向量