Research of NCL circuits parallel processing architecture

doi:10.3778/j.issn.1002-8331.2010.01.018

Computer Engineering and Applications ›› 2010, Vol. 46 ›› Issue (1): 54-56.DOI: 10.3778/j.issn.1002-8331.2010.01.018

• 研发、设计、测试 • Previous Articles Next Articles

Research of NCL circuits parallel processing architecture

CUI Ya-lei，DAI Zi-bin

Institute of Electronic Technology，the PLA Information Engineering University，Zhengzhou 450004，China

Received:2008-09-25 Revised:2008-12-25 Online:2010-01-01 Published:2010-01-01
Contact: CUI Ya-lei

NCL电路并行处理结构研究

崔亚磊，戴紫彬

解放军信息工程大学电子技术学院，郑州 450004

通讯作者: 崔亚磊

Abstract

Abstract: This paper proposes a framework of NCL circuits parallel processing for reducing the NCL data wave time.After the two dual-rail data waves through the parallel circuits，the next null data has been calculated，so，the data to data cycle time has been shortened.Taking the 4×4 multiplier for example，the circuits have been fabricated in 0.18 ?滋m CMOS process.In the case of non-pipelining module，TDD has reduced 32.9% and in the case of 2 stage pipelining module，TDD has reduced 33.2%.

Key words: Null Convention Logic（NCL） circuits, parallel processing, asynchronous circuits

摘要： 针对NCL电路数据编码方式的特点，提出了一种并行数据处理的NCL电路结构，通过同时对两路双轨编码数据流的并行处理，提前计算出下一个无效数据，缩短了无效数据维持时间。此结构应用到4×4乘法器的设计，采用COMS 0.18 ?滋m工艺，乘法器在非流水模式下和2级流水模式下分别进行了综合、布局布线和仿真，与传统NCL 4×4乘法器相比，无效数据维持时间分别缩短了32.9%和33.2%。

关键词: 零约束逻辑电路, 并行处理, 异步电路

CLC Number:

TP332

CUI Ya-lei，DAI Zi-bin. Research of NCL circuits parallel processing architecture[J]. Computer Engineering and Applications, 2010, 46(1): 54-56.

崔亚磊，戴紫彬. NCL电路并行处理结构研究[J]. 计算机工程与应用, 2010, 46(1): 54-56.

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Research of NCL circuits parallel processing architecture

NCL电路并行处理结构研究

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