Computer Engineering and Applications ›› 2021, Vol. 57 ›› Issue (5): 216-221.DOI: 10.3778/j.issn.1002-8331.2009-0011

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Implementation of Convolutional Neural Network SIP Microsystem

LYU Hao, ZHANG Shengbing, WANG Jia, LIU Shuo, JING Desheng   

  1. 1.School of Computer Science and Engineering, Northwestern Polytechnical University, Xi’an 710072, China
    2.Xi’an Aeronautics Computing Technique Research Institute, Aviation Industry Corporation of China, Xi’an 710065, China
  • Online:2021-03-01 Published:2021-03-02



  1. 1.西北工业大学 计算机学院,西安 710072
    2.中国航空工业集团公司 西安航空计算技术研究所,西安 710065


In recent years, microelectronics technology has entered the era of nanoelectronics/integrated microsystems. SIP(System in Package) and SOC(System on Chip) are two important technical approaches for the realization of microsystems. Deep learning technology based on neural network is widely used in computer vision and target recognition areas. How to combine lightweight neural network with micro system to achieve the optimal balance of performance, volume and power consumption is a difficult problem. The miniaturization of embedded platforms for deep learning technology of convolutional neural networks is an important research field. This article introduces a microsystem implementation scheme that combines SIP technology and FPGA-based convolutional neural network. It uses Zynq SOC, FLASH, and DDR3 memory as the main components, and uses SIP high-density system packaging technology for integration. The PL end(FPGA) uses HLS to design the convolutional layer and pooling layer in CNN(Convolutional Neural Network), generate IP cores, and time-multiplex to build a micro system. Micro_VGGNet lightweight model is designed and implemented. The test uses the MNIST handwritten digit data set as training and test samples. The microsystem can accurately recognize handwritten digits with an accuracy rate of 98.1%. The volume is only 30 mm×30 mm×1.2 mm, and the image processing speed can reach 20.65 FPS at a working frequency of 100 MHz. The power consumption is only 2.1 W. The multi-objective balance(performance, volume and power consumption) of lightweight neural network microsystem is realized.

Key words: microsystem, System in Package(SIP), Convolutional Neural Network(CNN), digit recognition


近年来,微电子技术进入到纳电子/集成微系统时代,SIP(System in Package)和SOC(System on Chip)是微系统实现的两种重要技术途径;基于神经网络的深度学习技术在图形图像、计算机视觉和目标识别等方面得以广泛应用。卷积神经网络的深度学习技术在嵌入式平台的小型化、微型化是一项重要研究领域。如何将神经网络轻量化和微系统相结合,达到性能、体积和功耗的最优化平衡是一难点。介绍了一款将SIP技术和基于FPGA的卷积神经网络相结合的微系统实现方案,它以Zynq SOC和FLASH、DDR3存储器为主要组成,利用SIP高密度系统封装技术进行集成,在其中的PL端(FPGA)采用HLS来设计CNN(Convolutional Neural Network,卷积神经网络)中的卷积层和池化层,生成IP核,分时复用构建微系统,设计实现了Micro_VGGNet轻量化模型。测试采用MNIST手写数字数据集作为训练和测试样本,该微系统能够实准确识别手写数字,准确率达到98.1%。体积仅为30 mm×30 mm×1.2 mm,在100 MHz工作频率下,?图像处理速度可达到20.65 FPS,功耗仅为2.1 W,实现了轻量化神经网络微系统的多目标平衡(性能、体积和功耗)。

关键词: 微系统, 系统级封装(SIP), 卷积神经网络(CNN), 数字识别