Abstract:

An optimized strategy is proposed for 3D System on Chip（SoC） parallel testing in the mid-bond test phase under power and multi-core test parallelism constraints. By reasonably allocating Test Access Mechanism（TAM）, test time is greatly reduced and test cost is also reduced. In the testing process of 3D SoC, the TAM resource of the chip is very limited. The method of this paper makes the core of each layer in test schedule in order by the number of testing TAM resources occupied. By designing the corresponding test wrapper structure, the idle TAM resources under the current state of the system and the internal scan chains of cores under test are redistributed, in order to make cores waiting for scheduling advance into test phase, and reduce idle time in parallel testing. On the basis of the structure, the scheduling sequence of each core is adjusted to make the test process meet all constraints. Experimental results show that compared with traditional methods, the method proposed in this paper reduces the test time more effectively.

Key words: 3D System on Chip（3D SoC）, Test Access Mechanism（TAM）, test wrapper, test scheduling, test time

摘要：

提出了一种在功耗及测试并行性约束下三维片上系统（System on Chip，SoC）绑定中测试阶段并行测试的优化策略，通过最大限度地利用测试访问机制（Test Access Mechanism，TAM）资源，大大减少了测试时间，降低了测试成本。在3D SoC的测试过程中系统TAM资源十分有限，通过设计相应的测试外壳结构，对系统当前状态下空闲的TAM资源与待测芯核内部扫描链进行重新分配，使待调度的芯核提前进入测试阶段，减少了并行测试过程中的空闲时间块。在该结构基础上调整各芯核调度顺序，使测试过程满足各项约束条件。在ITC’02电路上的实验结果表明，在同样的功耗约束及测试并行性约束条件下，所提方法与现有方法相比更有效地降低了测试时间。

关键词: 三维片上系统（3D SoC）, 测试访问机制（TAM）, 测试外壳, 测试调度, 测试时间