Computer Engineering and Applications ›› 2010, Vol. 46 ›› Issue (15): 60-63.DOI: 10.3778/j.issn.1002-8331.2010.15.019
• 研发、设计、测试 • Previous Articles Next Articles
ZHAO Jian-wu，SHI Yi-bing，WANG Zhi-gang
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赵建武，师奕兵，王志刚
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Abstract: One of the main problems for the test of an SoC is the test scheduling.In the paper，a test scheduling method of NoC-based SoC is used to minimize test time while addressing resource conflicts between shared test resources and power dissipation constraints.Both the routing algorithm and the test access chains optimal algorithm are developed to support the test scheduling.A 2D mesh topological NoC is described by using VHDL while being implemented in FPGA.The NoC test platform is developed to analyze the NoC performance parameters，routing algorithm and switching algorithm.Finally，The experimental results from NoC test platform are analyzed.
Key words: network-on-chips, System-on-Chip, embedded IP cores, test scheduling
摘要： 测试规划是SoC芯片测试中需要解决的一个重要问题。一种复用片上网络测试内嵌IP芯核的测试规划方法被用于限制测试模式下SoC芯片功耗不超出最大芯片功耗范围，消除测试资源共享所引起的冲突，达到减小测试时间的目的。提出了支持测试规划的无拥塞路由算法和测试扫描链优化配置方法。使用VHDL硬件描述语言实现了在FPGA芯片中可综合的二维Mesh片上网络测试平台，用于片上网络性能参数、路由算法以及基于片上网络的SoC芯片测试方法的分析评估。
关键词: 片上网络, 微系统芯片, 内嵌IP芯核, 测试规划
CLC Number:
TN407
ZHAO Jian-wu，SHI Yi-bing，WANG Zhi-gang. Research on test scheduling for SoC embedded IP cores based on reuse of network-on-chip[J]. Computer Engineering and Applications, 2010, 46(15): 60-63.
赵建武，师奕兵，王志刚. 复用NoC测试SoC内嵌IP芯核的测试规划研究 [J]. 计算机工程与应用, 2010, 46(15): 60-63.
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URL: http://cea.ceaj.org/EN/10.3778/j.issn.1002-8331.2010.15.019
http://cea.ceaj.org/EN/Y2010/V46/I15/60
