Abstract: With the increasing enhancement of chip indensity and progress of manufacture technology，new test methodologies and fault models need to be developed to meet the target of high test coverage and product yield.Scan-based at speed test is widely used in deep sub-micro SoC chip delay test.Through successful application of delay test for a high performance，complex mix-signal SoC chip，this paper describes the logic implementation of re-useable clock generation for delay test，delay test pattern generated by ATPG tool.High transition delay and path delay test coverage are achieved with low test cost，meet the requirement of fast time-to-market.

Key words: SoC, delay test, test coverage

摘要： 随着芯片集成度的持续提高以及制造工艺的不断进步，对测试覆盖率和产品良率的严格要求，需要研究新的测试方法和故障模型。基于扫描的快速延迟测试方法已经在深亚微米的片上系统（SoC）芯片中得到了广泛的使用。通过一款高性能复杂混合信号SoC芯片的延迟测试的成功应用，描述了从芯片对延迟测试的可复用的时钟产生逻辑的实现，到使用ATPG工具产生延迟图形，在相对较低的测试成本下，获得了很高的转换延迟和路径延迟故障覆盖率，满足了产品快速上市的要求。

关键词: 片上系统, 延迟测试, 测试覆盖率