Packets Forwarding Technology with Crossed Pipeline and Multi-queue Buffer

Computer Engineering and Applications ›› 2007, Vol. 43 ›› Issue (4): 150-152.

• 网络、通信与安全 • Previous Articles Next Articles

Packets Forwarding Technology with Crossed Pipeline and Multi-queue Buffer

Received:2006-03-07 Revised:1900-01-01 Online:2007-02-01 Published:2007-02-01

交叉流水线多队列缓冲报文转发技术

毛席龙孙志刚

长沙国防科大计算机学院网络所国防科学技术大学湖南长沙

通讯作者: 毛席龙

Abstract

Abstract: IP packets encapsulation as link layer frames is necessary to a router design. In this paper we present an universal processor architecture for multi-channel packets encapsulation and forwarding, combined with FPGA embedded memory blocks, pipeline and multi-queue buffer mechanism, which improved the capability of short packets forwarding at wire-speed or burst flow transfer.

Key words: Pipeline, Multi-queue, Packets Forwarding

摘要： IP报文封装为链路帧是路由器设计必不可少的技术。本文提出了一种通用的多通道报文封装和转发的处理器结构，利用FPGA内部存储资源，采用流水线和多队列缓存区相结合，显著提高了小报文线速转发和突发流量传输的性能。

关键词: 流水线, 多队列, 报文转发

毛席龙孙志刚. 交叉流水线多队列缓冲报文转发技术[J]. 计算机工程与应用, 2007, 43(4): 150-152.

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Packets Forwarding Technology with Crossed Pipeline and Multi-queue Buffer

交叉流水线多队列缓冲报文转发技术

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