Abstract: The “busy-wait” technology is often used to implement locks or barriers in shared memory multi-core processors.These synchronization mechanisms are restricted by the long latency and resource contention problems and are not scalable.They often need to access memory repeatedly and affect the normal memory accessing process.A synchronization technology based on the invalidation of instruction cache for the SDTA-based multi-core processor is proposed.At the synchronization point，the processor cores invalidate the corresponding instruction cachelines which cause instruction fetch miss.Then instruction fetch requests are issued to the L2 cache.The L2 cache adopts a filter mechanism to freeze those fetch requests to suspend the processor cores that need synchronization.The proposed mechanism is scalable and has a better performance.

Key words: Synchronous Data Triggered Architecture（SDTA）, multi-core processor, invalidation, synchronization

摘要： 共享存储多核处理器中“忙-等待”技术常用来实现锁或栅栏等同步操作，这些典型的同步机制通常受限于较长的同步延迟和资源竞争等问题，导致扩展性较差，且需要不时进行访存操作，影响正常存储器访问操作，加剧对存储系统的带宽需求。提出了一种用于同步数据触发结构多核处理器的基于指令Cache作废的同步技术，同步时作废将执行的指令Cache行导致取指失效，向L2 Cache发送取指请求，L2 Cache中设置相应的过滤机制，不服务不满足同步条件的处理器核的取指请求，使相应处理器核暂停，达到同步目的。测试表明，该方法在可扩展性和同步性能方面均具有一定的优势。

关键词: 同步数据触发结构, 多核处理器, 作废, 同步技术