Computer Engineering and Applications ›› 2018, Vol. 54 ›› Issue (15): 57-61.DOI: 10.3778/j.issn.1002-8331.1802-0052

Previous Articles     Next Articles

Single-bit compressed sensing for frame timing synchronization

WANG Wei, QING Chaojin, WAN Dongqin, YANG Qingyao   

  1. School of Electrical and Information Engineering, Xihua University, Chengdu 610039, China
  • Online:2018-08-01 Published:2018-07-26


王  维,卿朝进,万东琴,阳庆瑶   

  1. 西华大学 电气与电子信息学院,成都 610039

Abstract: The Compressed Sensing(CS)-based Frame Timing Synchronization(FTS) can reduce the energy consumption of communication systems and the design difficulty of the Analog-to-Digital Converter(ADC), compared with the non-CS FTS method. Instead of preserving the measurement amplitudes of CS-based technology, the single-bit CS technology only preserves measurements’ symbol information, and thus can further reduce the system’s energy consumption and the ADC’s design difficulty. In view of the above-mentioned advantages, the single-bit CS technology is introduced into FTS in this paper, and a single-bit CS based FTS method is proposed. Firstly, the proposed method performs single-bit compressive sampling on the received signal in the frame timing transformation domain. Subsequently, the timing metrics of frame timing synchronization are reconstructed by using the sampled bit stream. Finally, the index position of the FTS is found by searching the reconstructed timing metrics according to the correlation criterion. Compared with the CS-based FTS method, the analysis and simulation results show that the proposed method can improve the Correct Synchronization Probability(CSP) with the same bit overhead. Correspondingly, less bit overhead is needed in the proposed method with the same CSP. Meanwhile, the proposed method only requires a comparator in quantization phase, which reduces the design difficulty of ADC.

Key words: frame timing synchronization, single-bit compressed sensing, analog-to-digital converter, timing metrics(metrics)

摘要: 相对于非压缩感知帧定时同步方法,压缩感知帧定时同步方法可以降低系统的能量消耗,降低模拟数字转换器的设计难度。相对于压缩感知技术,单比特压缩感知仅保留观测值的符号信息,可进一步降低系统的能量消耗,降低模拟数字转换器的设计难度。为此,将单比特压缩感知技术引入到帧定时同步中,提出了一种基于单比特压缩感知的帧定时同步方法。提出方法首先在帧定时变换域对接收信号进行单比特的压缩采样;随后,利用采样到的比特流重构出用于帧定时同步的定时度量;最后,根据相关法帧定时同步准则,搜索重构到的定时度量,找到帧定时同步的索引位置。分析与仿真结果表明,相对于压缩感知帧定时同步方法,在相同的比特开销情况下,提出方法可改善帧定时同步的正确同步概率;在相同的正确同步概率情况下,提出方法所需比特数更少。同时,提出方法的量化过程仅需要电平比较器,降低了模拟数字转换器设计难度。

关键词: 帧定时同步, 单比特压缩感知, 模拟数字转换器, 定时度量