Abstract: In high-performance superscalar microprocessors, when long latency instructions reach the top of reorder buffer, instructions in the pipeline retire slowly. In this paper, a highly efficient retirement architecture is proposed, in which instructions can fast retire as soon as they are confirmed without exception and mis-prediction. Then results can be written back out of order. A result buffer is seperated from reorder buffer to achieve register renaming and out-of-order writing back. Reorder buffer is in charge of instructions’s in-order retirement and maintance of the precise exception. When the reorder buffer confirms that an instruction will not generate exception, this instruction fast retires from the reorder buffer and waits for the result in the result buffer. The experiment shows that in the condition of the same resource, the performance can be increased by 33% compared to the traditional architecture.

Key words: in-order retirement, Reorder Buffer（ROB）, fast retire, out-of-order write back

摘要： 针对超标量处理器中长延时的指令长时占用重排序缓存的顶端引起流水线退休缓慢的问题，提出了一种将无异常风险的指令快速退休并将运算结果乱序回写的高效退休机制。该方案将结果缓存器与重排序缓存分离，其中结果缓存器作为运算结果回写的缓存器，重排序缓存负责指令按序退休与精确异常的维护。重排序缓存单元在确认指令不会发生异常后，将指令从重排序缓存中快速退休，结果缓存器继续等待结果并进行乱序回写。实验结果表明，在硬件资源相同的情况下，通过提高重排序缓存器的使用效率，基于该方案的处理器相比于传统的按序退休处理器的性能平均提高33%。

关键词: 按序退休, 重排序缓存, 快速退休, 乱序回写