Computer Engineering and Applications ›› 2014, Vol. 50 ›› Issue (5): 208-211.

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Design of  DDS based on Taylor series and implementation in FPGA

XU Qi, DUAN Zhemin   

  1. School of Electronics and Information, Northwestern Polytechnical University, Xi’an 710072, China
  • Online:2014-03-01 Published:2015-05-12

泰勒级数的DDS设计与FPGA实现

徐  琪,段哲民   

  1. 西北工业大学 电子信息学院,西安 710072

Abstract: In this paper, in order to increase the output signal Spurious Free Dynamic Range(SFDR) of DDS, the method is that the phase dithered of DDS is reduced by the Taylor series and it is not to raise the width of the accumulator. The simulation for over a band of frequencies of DDS, having 32 bits width of the accumulator, is showed that the DDS with the Taylor series provides enhanced 12 dB better performance compared to it without Taylor series. This method has an importance practical value for DDS design.

Key words: Taylor series, Direct Digital Synthesis(DDS), Spurious Free Dynamic Range(SFDR), lookup table

摘要: 为了提高直接数字频率合成输出信号的动态范围,提出了一种在不增加直接数字频率合成中的累加器的位数的基础上,利用泰勒级数法较少数字频率合成的相位抖动的方法。并且对一个具有32位累加器的直接数字频率合成,输出一定频率范围的信号进行了仿真。仿真结果表明,基于泰勒级数的直接数字频率合成具有较好的动态范围,比一般的方法提高了12 dB。该方法对直接数字频率合成设计者有着重要的参考价值。

关键词: 泰勒级数, 直接数字频率合成(DDS), 动态范围, 查找表