Abstract: Based on TSMC 0.18 μm CMOS technology, a novel circuit topology for a CMOS Low-Noise-Amplifier（LNA） is presented in this paper. In this circuit, a cascode topology with inter-stage matching network is designed at the frequency of 5.8 GHz. Choosing a inter-stage matching network presents lower power dissipation while achieving reasonable power gain. In order to save the chip area, a LC network is used instead of the large inductor. The simulation results show the forward gain（S21） is about 10.3 dB, as well as less than －16 dB isolation（S12） while operating at 5.8 GHz. The input impedance（S11） and the output impedance（S22） also represent good performance. In addition, the minimum noise figure and signal linearity performance are quite good. It consumes only 12.7 mW under a 1.5 V voltage supply.

Key words: low noise amplifier, CMOS, noise figure, linearity

摘要： 基于0.18 μm CMOS工艺，设计了一个新型的低噪声放大器。在该放大器中，采用带有级间匹配的共源共栅结构。采用级间匹配结构实现了低功耗高增益。为了降低芯片面积，使用LC并联网络代替传统的大电感。仿真结果表明，在5.8 GHz的工作频率下，功率增益大约为10.3 dB，而反向隔离度低于－16 dB。同时具有比较好的输入输出匹配。除此之外，还获得了比较小的最小噪声系数和比较好的线性度。在1.5 V的供电电压下，电路的静态功耗为12.7 mW。

关键词: 低噪声放大器, CMOS, 噪声系数, 线性度