High performance VLSI architecture for 2D DWT

Computer Engineering and Applications ›› 2014, Vol. 50 ›› Issue (20): 187-191.

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High performance VLSI architecture for 2D DWT

SONG Youcai1, HAN Bo1，2, WANG Shibing1, TAN Fuxiao1, ZHAO Zhengping1

1.School of Computer and Information Engineering, Fuyang Teachers’ College, Fuyang, Anhui 236037, China
2.State Key Laboratory of Millimeter Waves, Southeast University, Nanjing 210096, China

Online:2014-10-15 Published:2014-10-28

高性能二维9/7离散小波变换VLSI结构

宋有才1，韩波1，2，王诗兵1，谭拂晓1，赵正平1

1.阜阳师范学院计算机与信息工程学院，安徽阜阳 236037
2.东南大学毫米波国家重点实验室，南京 210096

Abstract

Abstract: In order to reduce the memory size in 2-dimensional discrete wavelet transform and improve the processing speed, a parallel processing architecture is proposed. By analyzing the relationship between the row-transform core and the column-transform core, a modified parallel scanning method is presented. The temporal memory requirement for the 2-D 9/7 DWT are 4N. The flipping structure of 9/7 filter has been used to shorten the critical path to one multiplier delay. Moreover, through merging the scaling steps, the proposed VLSI architecture can reduce the amount of multipliers to 10, thereby effectively reducing the hardware consumption.

Key words: Discrete Wavelet Transform（DWT）, Very Large Scale Integration（VLSI） architecture, parallel scanning method, flipping structure

摘要： 为了降低二维小波变换中的存储消耗并同时提高电路处理速度，提出了一种二维并行的VLSI结构。通过充分挖掘二维变换中行变换和列变换之间的关系，优化了行变换核和列变换核的并行数据扫描输入方式，将9/7小波变换的中间存储降低至4N。同时，采用基于翻转格式的流水线技术，将电路的关键路径缩短至一级乘法器延时，有效地提高了电路处理速度，并通过伸缩电路合并的优化方法将乘法器个数降低至10个，从而有效地减少了硬件资源消耗。

关键词: 离散小波变换, 超大规模集成（VLSI）结构, 并行扫描, 翻转格式

SONG Youcai1, HAN Bo1，2, WANG Shibing1, TAN Fuxiao1, ZHAO Zhengping1. High performance VLSI architecture for 2D DWT[J]. Computer Engineering and Applications, 2014, 50(20): 187-191.

宋有才1，韩波1，2，王诗兵1，谭拂晓1，赵正平1. 高性能二维9/7离散小波变换VLSI结构[J]. 计算机工程与应用, 2014, 50(20): 187-191.

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High performance VLSI architecture for 2D DWT

高性能二维9/7离散小波变换VLSI结构

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