Computer Engineering and Applications ›› 2014, Vol. 50 ›› Issue (19): 78-84.

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Hierarchical architecture of RSA accelerator based on hardware resource reuse

ZHAO Kailan1, ZHANG Xiaoxu1, MA De2, HUANG Kai1, YAN Xiaolang1   

  1. 1.College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China
    2.Institute of Microelectronics CAD, Hangzhou Dianzi University, Hangzhou 310018, China
  • Online:2014-10-01 Published:2014-09-29


赵开兰1,张晓旭1,马  德2,黄  凯1,严晓浪1   

  1. 1.浙江大学 电气工程学院,杭州 310027
    2.杭州电子科技大学 微电子CAD所,杭州 310018

Abstract: To improve the performance of the RSA cryptography system for the application of modular frequent change, a novel hierarchical architecture of RSA accelerator is proposed. With hardware resource reuse with Montgomery Modular Multiplier, both modular inverse and [R2modM]arithmetic function are supported by the proposed accelerator to improve performance of RSA key generation and Montgomery Modular multiplication. As the experiment shows, compared with previous works, the performance of RSA accelerator is 2 times faster for the application of modular frequent change under 14% resource overhead. What’s more, the accelerator achieves one order of magnitude performance increasing for [R2modM]calculation comparing with the method of reusing Modular Exponentiation module.

Key words: RSA encryption algorithm, accelerate, hierarchical design, resource reuse

摘要: 为了解决RSA在模频繁变化情况下性能不足的问题,在已有蒙哥马利模乘器的基础上采用层次化架构设计复用硬件资源,实现了基于改进扩展欧几里德算法的偶数模逆器和[R2modM]运算器。实验结果显示,在14%的额外硬件资源开销下RSA加速器性能在模频繁变化应用下比原来提高2倍。其中,模逆器性能较其他设计提高了3倍,[R2modM]运算器性能比复用模幂电路的实现方法提高了一个数量级。

关键词: RSA加密算法, 加速, 层次化设计, 资源复用