### Hierarchical architecture of RSA accelerator based on hardware resource reuse

ZHAO Kailan1, ZHANG Xiaoxu1, MA De2, HUANG Kai1, YAN Xiaolang1

1. 1.College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China
2.Institute of Microelectronics CAD, Hangzhou Dianzi University, Hangzhou 310018, China
• Online:2014-10-01 Published:2014-09-29

### 基于资源复用的RSA加速器层次化架构

1. 1.浙江大学 电气工程学院，杭州 310027

Abstract: To improve the performance of the RSA cryptography system for the application of modular frequent change, a novel hierarchical architecture of RSA accelerator is proposed. With hardware resource reuse with Montgomery Modular Multiplier, both modular inverse and [R2modM]arithmetic function are supported by the proposed accelerator to improve performance of RSA key generation and Montgomery Modular multiplication. As the experiment shows, compared with previous works, the performance of RSA accelerator is 2 times faster for the application of modular frequent change under 14% resource overhead. What’s more, the accelerator achieves one order of magnitude performance increasing for [R2modM]calculation comparing with the method of reusing Modular Exponentiation module.