Abstract: Recently researches show that LDPC decoder design based on parallel layered decoding algorithm can achieve a higher throughput using a smaller chip area. A decoder hardware design method for this algorithm is proposed. This method uses shift register chain to reduce the required chip area of decoder design for parallel layered decoding algorithm further. The decoder hardware design is implemented in TSMC 65 nm process based on the rate-1/2 LDPC in IEEE 802.16e. The decoder design achieves a throughput of 1.2 Gb/s at 10 iterations with an chip area of 1.1 mm2. Puncturing technique is used to produce arbitrary rate between 1/2 and 1 in this decoder design.

Key words: LDPC decoder, quasi-cyclic codes, parallel layered decoding architecture, shift register chain

摘要： 基于并行分层译码算法的LDPC译码器可以使用较小的芯片面积实现较高的译码速率。提出一种基于该算法的译码器硬件设计方法。该设计方法通过使用移位寄存器链，来进一步降低基于并行分层译码算法的译码器芯片面积。该硬件设计使用TSMC 65 nm工艺实现，并在实现中使用IEEE 802.16e中的1/2码率LDPC码。该译码器设计在迭代次数设置为10次时可实现1.2 Gb/s的译码速率，芯片面积1.1 mm2。译码器设计通过打孔产生1/2至1之间的连续码率。

关键词: LDPC译码器, 准循环码, 并行分层译码结构, 移位寄存器链