Abstract: This paper presents an improved binary-to-binary logarithm and anti-logarithm line approximation including its VLSI implementation. This arithmetic can increase precision well, compared with the newest references, the logarithm converter’s percent error reduces 46.1 percent and the anti-logarithm converter’s percent error reduces 32.2 percent. A leading-one detector circuit is designed to obtain the leading-one position of an input binary word and error-correcting circuit is designed to reduce error. The implementation is simply, uses combinational logic only and calculates the approximation in a single clock cycle.

Key words: Logarithm/anti-logarithm converter Line approximation VLSI implementation

摘要： 本文提出一种二进制数的指数/对数运算的线性近似的改进算法，并VLSI实现。该算法能较好的提高精度，相比于现有最新文献提出的算法，对数运算的相对误差减少了46.1％，指数运算的相对误差减少了32.2％。实现时，设计了前导1探测电路和减小误差的误差补偿电路。该算法VLSI实现简单，只需组合逻辑就能在一个时钟周期内就能得到计算结果。

关键词: 对数/指数运算 线性近似 硬件实现