CAVLD architecture basing on fast algorithm

Computer Engineering and Applications ›› 2007, Vol. 43 ›› Issue (28): 99-102.

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CAVLD architecture basing on fast algorithm

HE Jun,TIAN Ying-hong,ZHOU Yang,HONG Zhi-Liang

ASIC & System State Key Laboratory,Fudan University,Shanghai 201203,China

Received:1900-01-01 Revised:1900-01-01 Online:2007-10-01 Published:2007-10-01
Contact: HE Jun

基于CAVLD快速算法的硬件实现

何俊,田应洪,周杨,洪志良

复旦大学专用集成电路与系统国家实验室,上海 201203

通讯作者: 何俊

Abstract

Abstract: The article proposes a fast decode method based on CAVLD,and presents a VLSI architecture design of the CAVLD.The experimental results show the proposed algorithm improves the performance of the CAVLD.

Key words: CAVLD, fast decode, lookup address, H.264/AVC

摘要： 在H.264的解码过程中,由于CAVLD部分采用的是变长编码,不能通过并行机制来提高速度,限制了整个系统的性能。针对CAVLD的硬件实现,提出一种新的算法,该算法采用地址查找法来提高解码速度,同时通过采用流水线结构,加快解码速度,采用计算方法代替查找表,减少ROM资源。FPGA综合结果表明最高速度支持到106 MHz,通过与文献[5]比较,解码速度提高12％～48％。

关键词: CAVLD, 快速解码, 地址查找, H.264/AVC

HE Jun,TIAN Ying-hong,ZHOU Yang,HONG Zhi-Liang. CAVLD architecture basing on fast algorithm[J]. Computer Engineering and Applications, 2007, 43(28): 99-102.

何俊,田应洪,周杨,洪志良. 基于CAVLD快速算法的硬件实现[J]. 计算机工程与应用, 2007, 43(28): 99-102.

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CAVLD architecture basing on fast algorithm

基于CAVLD快速算法的硬件实现

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