Abstract: The Aviation Microelectronic Center of NPU (Northwestern Polytechnical University ) has recently completed the development of a 32-bit super-scalar RISC microprocessor , which we call “Longtium” R2. In this paper we present the design of the Cache of “Longtium” R2, which we deem to be successful because it helps “Longtium” R2 to meet performance requirements. Section 1 shows the architecture of the “Longtium” R2. Fig. 1 gives the schematical diagram of the architecture of the “Longtium” R2. Section 2 discusses in detail L1 Cache. Fig. 2 explains the architecture of L1 instruction Cache. the key desing of L2 Cache is introduced in detail in section 3 ;Section 4 analyzes the Cache Coherent. Simulation and synthesis results are explained in section 5. Section 6 introduces the “Longtium”R2 CPU is fabricated in a 0.18um CMOS process. the die size of the chip is 4.1 mm×4.1 mm and the CPU operating frequency is at least 233MHz .

Key words: RISC, Cache, Cache Coherent

摘要： 合理的组织一个多级的高速缓冲存储器（Cache）是一种有效的减少存储器访问延迟的方法。本文提出了一种设计32位超标量微处理器Cache单元的结构，讨论了一级Cache、二级Cache设计中的关键技术，介绍了Cache一致性协议的实现，满足了“龙腾”R2微处理器芯片的设计要求。整个芯片采用0.18um CMOS工艺实现，芯片面积在4.1 mm×4.1 mm之内，微处理器核心频率超过233 MHz ，功耗小于1.5W。

关键词: 高速缓冲存储器, 一级Cache, 二级Cache, Cache一致性