Abstract: The design of existing spiking neural network accelerators pays too much attention to the functional integrity of the hardware level and lacks relevant collaborative optimization at the algorithm level to ensure hardware computing efficiency. In addition, traditional event-driven spiking neural network accelerators do not consider the ubiquitous spike jitter phenomenon in spiking neuron models, so they cannot support inhibitory spiking neural networks. In order to solve the above problems, a design method of a suppressive spiking neural network accelerator is proposed by combining software and hardware. At the software optimization level, through the analysis of the calculation redundancy of the spiking neural network, a corresponding approximate calculation method is proposed to reduce the calculation amount of the spiking neural network greatly; at the hardware design level, a calculation module to solve the problem of pulse jitter is proposed, and on this basis, a parallel computing structure suitable for the approximate computing method is designed. In order to verify the rationality of the design, the accelerator prototype FEAS is deployed on Xilinx ZC706 FPGA. The test results on mainstream datasets show that compared with the previous accelerator deployment of spiking neural networks, FEAS has achieved more than an order of magnitude performance improvement while maintaining 97.54% of the original model accuracy.

Key words: spiking neural network, event-driven, inhibitory neural network, approximation calculation, hardware accelerator

摘要： 现有脉冲神经网络加速器的设计过多关注于硬件层面的功能完备性，缺少算法层面的相关协同优化以保证硬件计算效率。此外，传统的事件驱动型脉冲神经网络加速器没有考虑到脉冲神经元模型中普遍存在的脉冲抖动现象，因此不能实现对抑制型脉冲神经网络的支持。为解决上述问题，采用软硬件结合的方式，提出了一种支持抑制型脉冲神经网络加速器的设计方法。软件优化层面通过对脉冲神经网络计算冗余性的分析，提出了相应的近似计算方法以大幅降低脉冲神经网络的计算量；硬件设计层面提出了解决脉冲抖动问题的计算模块，并在此基础上设计了与近似计算方法相适应的并行计算结构。为验证设计的合理性，在Xilinx ZC706 FPGA上部署了加速器原型FEAS。在主流数据集上的测试结果显示，相较以往脉冲神经网络的加速器部署，FEAS在保持97.54%原有模型精度的情况下获得超过一个数量级的性能提升。

关键词: 脉冲神经网络, 事件驱动, 抑制型网络, 近似计算, 硬件加速器