Computer Engineering and Applications ›› 2023, Vol. 59 ›› Issue (23): 63-72.DOI: 10.3778/j.issn.1002-8331.2301-0102

• Theory, Research and Development • Previous Articles     Next Articles

Research on Code Detection and DFG Generation in CRCLA Compiler Front-End

YANG Chenguang, LI Wei, DU Yiran   

  1. School of Cryptography Engineering, Information Engineering University, Zhengzhou  450001, China
  • Online:2023-12-01 Published:2023-12-01

CRCLA编译前端中代码检测与DFG生成技术研究

杨晨光,李伟,杜怡然   

  1. 战略支援部队信息工程大学 密码工程学院,郑州 450001

Abstract: Aiming at the requirement of automatic mapping of cryptographic algorithms to reconfigurable cryptographic logic array(CRCLA) and providing accurate and concise data flow graph for back-end mapping, a front-end design of data flow graph generation and optimization is proposed. In this design, Flex and Bison are used as the compiler framework. The syntax tree is obtained by lexical and syntactic analysis of the code written by the high-level language C++, and the data flow graph is generated by semantic analysis according to the instruction characteristics of cryptographic algorithm and the hardware structure of CRCLA. There are functions implemented in different ways in the source code, such as S-box replacement and bit replacement, but they can be implemented in CRCLA instead of single operator. In order to solve such problems, this paper designs a graph embedding model based on attention mechanism for detection and recognition, and carries out graph structure replacement. At the same time, function expansion, redundant node elimination and data flow graph layering are used to optimize the data flow graph. The experimental results show that the simplified data flow graph is generated automatically after code identification and optimization, and the performance is improved by about 37% compared with other compiler front-end.

Key words: reconfigurable cryptographic logic array, front end, lexical syntax analysis, data flow graph, attention mechanism, graph embedding

摘要: 针对密码算法自动映射到可重构密码逻辑阵列(CRCLA)的需求,并为给后端映射提供准确、精简的数据流图,提出了一种数据流图生成与优化的前端设计。该前端以Flex、Bison为编译框架,对高级语言C++编写的代码进行词法、语法分析得到语法树,并依据密码算法指令特点和CRCLA硬件结构进行语义分析生成数据流图;源代码中存在不同方式实现的功能如S盒替换、比特置换,但其在CRCLA中可用单算子代替实现。设计了基于注意力机制的图嵌入模型进行检测识别,并进行图结构替换;同时函数展开、冗余节点消除与数据流图分层等操作优化了数据流图。实验结果表明,该设计经代码识别、优化后,实现了精简的数据流图自动化生成,与其他编译器的编译前端相比性能提高了约37%。

关键词: 可重构密码逻辑阵列, 前端, 词法语法分析, 数据流图, 注意力机制, 图嵌入