Computer Engineering and Applications ›› 2010, Vol. 46 ›› Issue (18): 74-76.DOI: 10.3778/j.issn.1002-8331.2010.18.024
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YANG Zhi-feng1,TIAN Ze2
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杨智峰1,田 泽2
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Abstract: The challenge of interconnection architecture based on bus is more and more serious,with the increase of complexity of SoC.In such background,the NoC with the characteristic of network interconnection has emerged as the times required.The paper analyzes several important criterions of NoC performance.Several criterions of NoC topologies with NS2(the network simulator) are evaluated.Finally,an instructive conclusion is drawn when design a NoC.Trade-offs with regard to several criterions of performance are explored,such as delay,throughput,area,power dissipation and re-usability in the NoC design and a proper architecture is choosen.
Key words: Network on Chip(NoC), Network Simulator-Version 2(NS2), delay, throughput, topology
摘要: 随着SoC复杂度的不断提高,总线互连结构面临着越来越严峻的挑战,因此,以网络互连为特点的NoC应运而生。分析了影响NoC性能的几项重要指标,并用网络仿真软件NS2对几种常用拓扑结构的几项性能参数进行了评估,得出了在进行NoC设计时的指导性结论:结合具体的设计,对传输延迟、吞吐量、面积、功耗和可重用性等性能参数进行折衷考虑后选取合适的体系结构。
关键词: 片上网络(NoC), NS2网络模拟器, 延迟, 吞吐量, 拓扑
CLC Number:
TN47
YANG Zhi-feng1,TIAN Ze2. Performance evaluation of NoC architectures using NS2[J]. Computer Engineering and Applications, 2010, 46(18): 74-76.
杨智峰1,田 泽2. 用NS2评估片上网络体系结构的性能[J]. 计算机工程与应用, 2010, 46(18): 74-76.
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URL: http://cea.ceaj.org/EN/10.3778/j.issn.1002-8331.2010.18.024
http://cea.ceaj.org/EN/Y2010/V46/I18/74