Direct digital frequency synthesizer based on improved CORDIC module

doi:10.3778/j.issn.1002-8331.2010.17.016

Computer Engineering and Applications ›› 2010, Vol. 46 ›› Issue (17): 57-59.DOI: 10.3778/j.issn.1002-8331.2010.17.016

• 研发、设计、测试 • Previous Articles Next Articles

Direct digital frequency synthesizer based on improved CORDIC module

CHEN Li-gong，SONG Xue-rui，WANG Xin

Information Science and Engineering College，Central South University，Changsha 410083，China

Received:2009-04-01 Revised:2009-06-08 Online:2010-06-11 Published:2010-06-11
Contact: CHEN Li-gong

改进的CORDIC模块实现的直接数字频率合成器

陈立功，宋学瑞，王鑫

中南大学信息科学与工程学院，长沙 410083

通讯作者: 陈立功

Abstract

Abstract: An improved algorithm based on the traditional fixed-point pipelined CORDIC-based algorithm is proposed to reduce number of iterations and realize the sign prediction in parallel processing.Improved algorithm not only greatly reduces the pipeline iterations but also saves the number of Slice Flip Flops of FPGA.Finally using this algorithm the Direct Digital frequency Synthesizer（DDS） at Xilinx’s Virtex-II platform is realized.

Key words: COordinate Rotation DIgital Computer（CORDIC）, Field Programmable Gate Array（FPGA）, sign prediction, Direct Digital frequency Synthesizer（DDS）

摘要： 在传统的定点数流水线型CORDIC算法基础上，就减少迭代次数上提出一种改进算法，实现并行处理时的符号预测。改进算法大大减少了流水线迭代次数，节省了FPGA的Slice Flip Flops数量。最后利用改进算法在Xilinx公司的Virtex-II平台上实现了直接数字频率合成器（DDS）。

关键词: 坐标旋转数字计算算法（CORDIC）, 现场可编程门阵列（FPGA）, 符号预测, 直接数字频率合成器（DDS）

CLC Number:

TN92

CHEN Li-gong，SONG Xue-rui，WANG Xin. Direct digital frequency synthesizer based on improved CORDIC module[J]. Computer Engineering and Applications, 2010, 46(17): 57-59.

陈立功，宋学瑞，王鑫. 改进的CORDIC模块实现的直接数字频率合成器[J]. 计算机工程与应用, 2010, 46(17): 57-59.

[1]	LENG Ming, SUN Lingyu, GUO Chen. Forward Circuit Generation Algorithm of XDL Netlist [J]. Computer Engineering and Applications, 2021, 57(10): 75-80.
[2]	WU Yiyang, FAN Fan, ZHOU Yi, HUANG Jun. FPGA Implementation of Affine Transformation Based on Pre-interpolation [J]. Computer Engineering and Applications, 2020, 56(6): 224-230.
[3]	ZHANG Wei, LIU Yuhong, ZHANG Rongfen. Design of IP Cores for CNN Convolutional Layer and Pooling Layer Capable of Time Division Multiplexing [J]. Computer Engineering and Applications, 2020, 56(24): 66-71.
[4]	WU Jin, ZHANG Weihua, XI Meng, DAI Wei. Optimized Design and FPGA Implementation of High-Performance Face Recognition Accelerator [J]. Computer Engineering and Applications, 2020, 56(22): 48-54.
[5]	WANG Fan, ZHOU Guoqing, ZHANG Rongting, LIU Dequan. FPGA-Oriented Fast Connected Component Labeling Method [J]. Computer Engineering and Applications, 2020, 56(22): 230-235.
[6]	LI Zenggang, WANG Zhengyan, SUN Jingcheng. Research and Design of Handwritten Digital BP Neural Network Based on FPGA [J]. Computer Engineering and Applications, 2020, 56(17): 251-257.
[7]	LI Rengang, REN Zhixin, WANG Jiangwei, KAN Hongwei, ZHANG Chuang, GONG Weifeng. Design and Implementation of Memory Data Protection Technology Based on FPGA [J]. Computer Engineering and Applications, 2020, 56(13): 72-76.
[8]	SUN Jingcheng, WANG Zhengyan, LI Zenggang. FPGA Implementation of Convolution Neural Network Digital Recognition System [J]. Computer Engineering and Applications, 2020, 56(13): 181-188.
[9]	WANG Haiyu, XIE Lili, WANG Shan. Neural Network Sinusoidal Signal Generator [J]. Computer Engineering and Applications, 2019, 55(16): 259-264.
[10]	WANG Weiting1，2, LI Jinjie2, ZHANG Wenxu1. Research of implementing DDS without phase truncation spur based on phase code compensation [J]. Computer Engineering and Applications, 2017, 53(4): 244-250.
[11]	FENG Binbin1, JIANG Xinhua1，2, LIN Junjie2, NIE Mingxing2. Research and implementation of real-time semi global matching algorithm based on FPGA stereo vision [J]. Computer Engineering and Applications, 2017, 53(22): 163-168.
[12]	ZHANG Xiaonan1, GAO Xianwei1，2, DONG Xiuze2. Improvement and implementation of carry-save large numbers multiplication on FPGA [J]. Computer Engineering and Applications, 2017, 53(21): 58-61.
[13]	LI Yan, CUI Haoxin, DU Yongbin. Hardware implementation of two-level scheduling algorithm of μC/OS-II [J]. Computer Engineering and Applications, 2016, 52(12): 1-4.
[14]	FANG Rui, LIU Jiahe, XUE Zhihui, YANG Guangwen. FPGA-based design for convolution neural network [J]. Computer Engineering and Applications, 2015, 51(8): 32-36.
[15]	YANG Dawei, ZHAN Zhenqiang, LI Encheng. Scheme of vehicle infrared night vision projection system [J]. Computer Engineering and Applications, 2015, 51(8): 153-155.

Direct digital frequency synthesizer based on improved CORDIC module

改进的CORDIC模块实现的直接数字频率合成器

PDF

Knowledge

Abstract

Cite this article

share this article

References

Related Articles 15

Recommended Articles

Metrics