Computer Engineering and Applications ›› 2010, Vol. 46 ›› Issue (15): 69-71.DOI: 10.3778/j.issn.1002-8331.2010.15.021
• 研发、设计、测试 • Previous Articles Next Articles
HUANG Xuan,CHEN Jie,ZHOU Li,LIU Zhen-yu
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黄 玄,陈 杰,周 莉,刘振宇
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Abstract: This paper presents a novel architecture of Variable Length Decoder(VLD) for AVS and MPEG2 decoders.The decoding of one AVS or MPEG2 VLD word can be carried out in one cycle with the reusable architecture.By reusing VLD controller and using combinational logic of look up table(LUT),the memory for storing AVS table can be avoided and circuit scale is reduced.For 0.18 μm CMOS process,the working frequency of the proposed VLD decoder reaches 166MHz with 9k logic gates and 3 kbit ROM.
Key words: Audio Video Coding Standard(AVS), MPEG-2, Exp-Golomb code, Variable Length Decoder(VLD), High Definition Television(HDTV)
摘要: 针对高清视频AVS和MPEG2解码系统,提出一种新的可复用的熵解码电路。该电路采用复用的结构,每个周期内完成一个AVS/MPEG2码字的解码;采用组合逻辑映射查表技术,不需要存储AVS码表;通过复用解码控制电路,减小了面积。对该模块进行了仿真和综合,在0.18微米工艺下,频率为166 MHz,面积为9k等效逻辑门,存储器使用量为3 kbit ROM。
关键词: 音视频编码标准(AVS), MPEG-2, 指数哥伦布码, 可复用的熵解码电路(VLD), 高清晰度电视(HDTV)
CLC Number:
TN919.81
HUANG Xuan,CHEN Jie,ZHOU Li,LIU Zhen-yu. Architecture and VLSI implementation of VLD for AVS and MPEG-2[J]. Computer Engineering and Applications, 2010, 46(15): 69-71.
黄 玄,陈 杰,周 莉,刘振宇. AVS和MPEG-2熵解码结构与电路实现[J]. 计算机工程与应用, 2010, 46(15): 69-71.
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URL: http://cea.ceaj.org/EN/10.3778/j.issn.1002-8331.2010.15.021
http://cea.ceaj.org/EN/Y2010/V46/I15/69