Abstract: A new method of implementing high order FIR filter with FPGA is presented.This method divides high order FIR filter into some lower order FIR filters by using polyphase decomposition structure，and implements the lower order FIR filters with modifying Distributed Arithmetic.A series of FIR filters which orders form 8 to 1，024 is designed.These proposed filters have been simulated and synthesized with Quartus II 7.1，implemented with an EP2S60F1020C4 FPGA device.Results show that the proposed method can implement FIR filters with the smaller resource usage and high speed.

摘要： 提出一种新的高阶FIR滤波器的FPGA实现方法。该方法运用多相分解结构对高阶FIR滤波器进行降阶处理，采用改进的分布式算法来实现降阶后的FIR滤波器。设计了一系列阶数从8到1 024的FIR滤波器，通过Quartus II 7.1的综合与仿真，以及在EP2S60F1020C4 FPGA目标器件上的实现结果表明，该方法能够有效地减少硬件资源的使用且满足高速实时性的要求。