Computer Engineering and Applications ›› 2009, Vol. 45 ›› Issue (32): 63-64.DOI: 10.3778/j.issn.1002-8331.2009.32.020

• 研发、设计、测试 • Previous Articles     Next Articles

Design and application of RapidIO chain

HUANG Xian-chun1,HUANG Deng-shan1,LUO Yan-bo2   

  1. 1.School of Electronics and Information,Northwestern Polytechnical University,Xi’an 710072,China
    2.The Telecommunication Engineering Institute,Air Force Engineering University,Xi’an 710077,China
  • Received:2008-09-11 Revised:2008-12-08 Online:2009-11-11 Published:2009-11-11
  • Contact: HUANG Xian-chun

RapidIO链的设计方案和应用

黄先春1,黄登山1,骆艳卜2   

  1. 1.西北工业大学 电子信息学院,西安 710072
    2.空军工程大学 电讯工程学院,西安 710077
  • 通讯作者: 黄先春

Abstract: SRIO(Serial RapidIO) supports two work modes:Message and DirectIO.The DirectIO mode is simple to operate,but in multi-packets transmission case,DSP CPU must wait until LSU(Load and Save unit) register is free.To solve this problem,the paper presents a new transimission way named RapidIO chain,which uses EDMA(Enhanced Direct Memory Access) channel instead of CPU to configure LSU registers of SRIO.Results of experiment show that RapidIO chain can reduce CPU load effectively.

Key words: Serial RapidIO(SRIO), Enhanced Direct Memory Access(EDMA), CPU load

摘要: 串行RapidIO支持两种工作方式:Message和DirectIO方式。DirectIO方式使用简单,但是它在连续传输多包的情况下,CPU需要等待LSU寄存器空闲。为了解决该问题,提出了RapidIO链的传输新方案,即用EDMA通道代替CPU配置SRIO的LSU寄存器。实验表明该方案能有效地降低CPU负荷。

关键词: 高速串行IO口(SRIO), 增强型内存直接存取(EDMA), CPU负荷

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