| [1] |
LENG Ming, SUN Lingyu, GUO Chen.
Forward Circuit Generation Algorithm of XDL Netlist
[J]. Computer Engineering and Applications, 2021, 57(10): 75-80.
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| [2] |
WU Yiyang, FAN Fan, ZHOU Yi, HUANG Jun.
FPGA Implementation of Affine Transformation Based on Pre-interpolation
[J]. Computer Engineering and Applications, 2020, 56(6): 224-230.
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| [3] |
ZHANG Wei, LIU Yuhong, ZHANG Rongfen.
Design of IP Cores for CNN Convolutional Layer and Pooling Layer Capable of Time Division Multiplexing
[J]. Computer Engineering and Applications, 2020, 56(24): 66-71.
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| [4] |
WU Jin, ZHANG Weihua, XI Meng, DAI Wei.
Optimized Design and FPGA Implementation of High-Performance Face Recognition Accelerator
[J]. Computer Engineering and Applications, 2020, 56(22): 48-54.
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| [5] |
WANG Fan, ZHOU Guoqing, ZHANG Rongting, LIU Dequan.
FPGA-Oriented Fast Connected Component Labeling Method
[J]. Computer Engineering and Applications, 2020, 56(22): 230-235.
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| [6] |
LI Zenggang, WANG Zhengyan, SUN Jingcheng.
Research and Design of Handwritten Digital BP Neural Network Based on FPGA
[J]. Computer Engineering and Applications, 2020, 56(17): 251-257.
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| [7] |
LI Rengang, REN Zhixin, WANG Jiangwei, KAN Hongwei, ZHANG Chuang, GONG Weifeng.
Design and Implementation of Memory Data Protection Technology Based on FPGA
[J]. Computer Engineering and Applications, 2020, 56(13): 72-76.
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| [8] |
SUN Jingcheng, WANG Zhengyan, LI Zenggang.
FPGA Implementation of Convolution Neural Network Digital Recognition System
[J]. Computer Engineering and Applications, 2020, 56(13): 181-188.
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| [9] |
WANG Haiyu, XIE Lili, WANG Shan.
Neural Network Sinusoidal Signal Generator
[J]. Computer Engineering and Applications, 2019, 55(16): 259-264.
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| [10] |
WANG Weiting1，2, LI Jinjie2, ZHANG Wenxu1.
Research of implementing DDS without phase truncation spur based on phase code compensation
[J]. Computer Engineering and Applications, 2017, 53(4): 244-250.
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| [11] |
FENG Binbin1, JIANG Xinhua1，2, LIN Junjie2, NIE Mingxing2.
Research and implementation of real-time semi global matching algorithm based on FPGA stereo vision
[J]. Computer Engineering and Applications, 2017, 53(22): 163-168.
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| [12] |
ZHANG Xiaonan1, GAO Xianwei1，2, DONG Xiuze2.
Improvement and implementation of carry-save large numbers multiplication on FPGA
[J]. Computer Engineering and Applications, 2017, 53(21): 58-61.
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| [13] |
LI Yan, CUI Haoxin, DU Yongbin.
Hardware implementation of two-level scheduling algorithm of μC/OS-II
[J]. Computer Engineering and Applications, 2016, 52(12): 1-4.
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| [14] |
YANG Dawei, ZHAN Zhenqiang, LI Encheng.
Scheme of vehicle infrared night vision projection system
[J]. Computer Engineering and Applications, 2015, 51(8): 153-155.
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| [15] |
FANG Rui, LIU Jiahe, XUE Zhihui, YANG Guangwen.
FPGA-based design for convolution neural network
[J]. Computer Engineering and Applications, 2015, 51(8): 32-36.
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