关键词: 误差扩散, 调频挂网, 高速, 查找表, 流水线

Abstract: Among many methods to digital FM halftone process，the error diffusion algorithm is a very good one，but unfortunately it is computationally costly and uses much memory access．The processing speed is the main bottlenecks of its extensive use．This paper approaches a high speed error diffusion chip to accelerate the speed of the process．The design uses some techniques such as LUT（Look Up Table），hierarchical storage system and the pipelined architecture to speed up the process，finally it can process average one pixel per clock cycle．At last the chip is implemented in FPGA and shows that it solves the speed bottleneck of the error diffusion FM screening in high speed equipment．

Key words: error diffusion, FM screening, high speed, LUT, pipeline