Abstract:

The XDL（Xilinx Design Language） netlist description file, which describes the FPGA（Field Programmable Gate Array） netlist, is not only used to parse for the extraction of the instance and net inside FPGA design, but also used to generate the forward circuit as the signal propagation model of FPGA netlist. This paper adopts the directed hyper-graph to describe the FPGA internal signal forward topology, whose vertex can be considered as the in-use pin of instance and directed hyper-edge can be represented as the net connection or the instance function between the in-use pins of instance. Furthermore, This paper not only gives the EBNF expression of the XDL compiler, but also presents the forward circuit generation algorithm of XDL netlist based on the directed hyper-graph, and analyzes the time and space complexity of the proposed algorithm. Finally, This paper implements the algorithm in Windows OS and Java based on the source code of RapidSmith software. The experiment of the test bench of Virtex-4 shows that the algorithm can generate the forward circuit from the XDL netlist description file. The correctness and effectiveness of the generation algorithm based on the directed hyper-graph is also proved by the experiment.

Key words: Field Programmable Gate Array（FPGA）, XDL netlist description file, directed hyper-graph, forward circuit

摘要：

作为描述FPGA（Field Programmable Gate Array）电路网表的XDL（Xilinx Design Language）描述文件，不仅能用于解析抽取FPGA设计的Inst电路单元和Net电路信号，而且能用于构建FPGA电路网表中信号传播的前向电路图模型。采用有向超图来构建FPGA电路网表中信号的前向拓扑关系，其中FPGA电路单元的有效管脚表示为超图结点，管脚间的外部连线、管脚内的电路逻辑功能表示为有向超边。给出了XDL网表级电路描述文件编译所需的EBNF表达式，提出了基于有向超图的XDL网表的前向电路图生成算法，进行了算法的时空复杂度分析。在Windows平台下基于RapidSmith开源软件实现了前向电路图生成算法，并选用基于Virtex-4型号FPGA测试用例的XDL网表，生成相应的前向电路图以验证XDL网表的前向电路图生成算法的正确性和有效性。

关键词: 现场可编程门阵列（FPGA）, XDL网表描述文件, 有向超图, 前向电路图